Abstract: A data transmission boosting device which can receive a plurality of data packets generated by terminal devices and connect to the router. The data transmission boosting device includes a classifying module which stores a classifying model, and the classifying model includes a plurality of classifying features. The classifying module can classify the type of each data packets by the classifying model and the packet information of data packets. The data transmission boosting device transmits the data packets classified as the data packets for boosting to the boosting server through the router. The data transmission boosting device of the present invention not only can improve the transmission efficient by the classifying module, but also can save the network flow cost.

Abstract: A bit-scale memory correcting method comprises steps: providing a memory with a plurality of memory bytes each having M bits, wherein M is a positive integer; adding a correcting byte to each memory byte, wherein the correcting byte has N correcting bits, and wherein N is a positive integer and smaller than M; detecting whether there is any underperforming bit in all the memory bytes and correcting bytes; if no, terminating memory correction; if yes, using the non-underperforming bits of the correcting byte to replace the underperforming bits of the memory byte, wherein the quantity of the non-underperforming bits of the correcting byte is corresponding to the quantity of the underperforming bits of the memory byte. The present invention proposes a simple and fast memory bit correcting method to decrease the redundant bits for correcting memory bits.

Abstract: A memory correcting method includes steps: providing a memory with a plurality of memory bytes; respectively adding a plurality of correcting bytes to the plurality of memory bytes; providing a plurality of non-volatile compared memory bytes; detecting whether there are any underperforming bits in the plurality of memory bytes, the plurality of correcting bytes, and the plurality of compared memory bytes of the memory to complete the correction. Alternatively, the method respectively provides a plurality of compared memory address bytes for the plurality of memory bytes and for the plurality of correcting bytes for labeling underperforming-bit addresses. Then, the method detects whether there are any underperforming bits in the plurality of memory bytes, the plurality of correcting bytes, and the plurality of compared memory address bytes of the memory to complete the correction.

Abstract: A semiconductor device is provided. The device includes a substrate having a first conductivity type. The device further includes a drain region, a source region, and a well region disposed in the substrate. The well region is disposed between the drain region and the source region and having a second conductivity type opposite to the first conductivity type. The device further includes a plurality of doped regions disposed within the well region. The doped regions are vertically and horizontally offset from each other. Each of the doped regions includes a lower portion having the first conductivity type, and an upper portion stacked on the lower region and having the second conductivity type.

Abstract: Media enhanced mobile payments enable a user to make payments and payment requests that include additional media. The user may transmit a text-based message that may be used to update an account associated with a recipient. Additional media, such as a personalized voice recording, may be acquired by a host from the user, and may be associated with the text-based message. The additional media may be transmitted to the recipient identified in the text-based message. In some aspects, the text-based message may be a short messaging service (SMS) text message. Further aspects may include the host connecting to the user via a telephone call to record the personalized voice recording.

Abstract: A memory correcting method includes steps: providing a memory with a plurality of memory bytes; respectively adding a plurality of correcting bytes to the plurality of memory bytes; providing a plurality of non-volatile compared memory bytes; detecting whether there are any underperforming bits in the plurality of memory bytes, the plurality of correcting bytes, and the plurality of compared memory bytes of the memory to complete the correction. Alternatively, the method respectively provides a plurality of compared memory address bytes for the plurality of memory bytes and for the plurality of correcting bytes for labeling underperforming-bit addresses. Then, the method detects whether there are any underperforming bits in the plurality of memory bytes, the plurality of correcting bytes, and the plurality of compared memory address bytes of the memory to complete the correction.

Abstract: A bit-scale memory correcting method comprises steps: providing a memory with a plurality of memory bytes each having M bits, wherein M is a positive integer; adding a correcting byte to each memory byte, wherein the correcting byte has N correcting bits, and wherein N is a positive integer and smaller than M; detecting whether there is any underperforming bit in all the memory bytes and correcting bytes; if no, terminating memory correction; if yes, using the non-underperforming bits of the correcting byte to replace the underperforming bits of the memory byte, wherein the quantity of the non-underperforming bits of the correcting byte is corresponding to the quantity of the underperforming bits of the memory byte. The present invention proposes a simple and fast memory bit correcting method to decrease the redundant bits for correcting memory bits.

Abstract: A semiconductor device is provided. The device includes a substrate having a first conductivity type. The device further includes a drain region, a source region, and a well region disposed in the substrate. The well region is disposed between the drain region and the source region and having a second conductivity type opposite to the first conductivity type. The device further includes a plurality of doped regions disposed within the well region. The doped regions are vertically and horizontally offset from each other. Each of the doped regions includes a lower portion having the first conductivity type, and an upper portion stacked on the lower region and having the second conductivity type.

Abstract: Techniques and apparatuses for providing wallet server information to an entity using a real-time mobile wallet server (MWS) are disclosed herein. The MWS may receive a request for personal information from an entity. The MWS may then display to a user a summary of the request, a list of selections available in the wallet server that may satisfy the request, and a list of selectable response options for the user to choose to respond to the entity. In some aspects, the wallet server may store username and associated passwords, payment information, and/or contact information. In further aspects, the MWS may generate limited-use payment information associated with existing payment information. The MWS may communicate ad hoc messaging to the entity using voice-based or real-time text-based communications over an established communication link between the MWS and entity.

Abstract: A semiconductor device is provided. The device includes a substrate having a first conductivity type. The device further includes a drain region, a source region, and a well region disposed in the substrate. The well region is disposed between the drain region and the source region and having a second conductivity type opposite to the first conductivity type. The device further includes a plurality of doped regions disposed within the well region. The doped regions are vertically and horizontally offset from each other. Each of the doped regions includes a lower portion having the first conductivity type, and an upper portion stacked on the lower region and having the second conductivity type.

Abstract: Various embodiments of a system and method for message-based purchasing are described. The system and method for message-based purchasing may include a message-based purchase service configured to determine that a selection has been performed through a network-based interface. Such selection may be indicative of one or more items offered for sale via the network-based interface. The message-based purchase service may be configured to, in response to the selection of one or more items, send to a communication device, a message indicating a code corresponding to the selection. The message-based purchase service may receive from the communication device through a communication channel that does not include the network-based interface, a message including the code. The message-based purchase service may be configured to, in response to determining that the message received from the communication device includes the code, generate a purchase request for the one or more previously selected items.

Abstract: System and method for authorizing transactions, such as payments or money transfers. A source entity may initiate a transaction with a target entity via a first communications channel. In initiating the transaction, the source entity may indicate that the transaction is to be performed through a transaction authorization service. The target entity may send a transaction initiation message to the transaction authorization service. In response to receiving the transaction initiation message, the service may authorize the transaction with the source entity via a second communications channel. To authorize the transaction, the source entity may provide a PIN number or other identifier via the second communications channel. After receiving and validating the response from the source entity, the transaction authorization service may inform the target entity that the transaction is authorized. The target entity may then complete the transaction with the transaction authorization service and the source entity.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate having an isolation region and an active region defined by the isolation region. At least one trench is formed in the active region and extends along a first direction. A gate layer is disposed on the active region and extends along a second direction, wherein the gate layer conformably fills the at least one trench and covers a bottom surface and sidewalls of the at least one trench. The disclosure also provides a method for manufacturing the semiconductor device.

Abstract: A mobile payment network receives location information from mobile devices used to conduct transactions between two account holders, and qualifies any requested transactions based on the physical proximity of the two devices relative to each other.

Abstract: A lateral diffused semiconductor device is disclosed, including: a substrate; a first isolation and a second isolation comprising at least portions disposed in the substrate to define an active area; a first drift region and a second drift region disposed in the active area, wherein the first drift region is disposed in the second drift region; a gate structure on the substrate; a source region in the first drift region; a drain region in the second drift region; and a ring-shaped field plate on the substrate, wherein the ring-shaped field plate surrounds at least one of the source and the drain region.

Abstract: An electronic device is provided, including a housing having a side wall, a display panel, a push latch, a video/audio transceiver, and an elastic member, wherein the display panel is disposed in the housing. The push latch is fixed on the housing. The video/audio transceiver is movably disposed in the housing, and has a connecting portion. The elastic member connects the video/audio transceiver with the housing. When the connecting portion is connected to the push latch, the video/audio transceiver is in a first position. When the connecting portion is separated from the push latch, the video/audio transceiver moves from the first position to a second position and protrudes from the side wall due to the elastic force of the elastic member.

Abstract: A semiconductor device is provided. The device includes a substrate having a first conductivity type. The device further includes a drain region, a source region, and a well region disposed in the substrate. The well region is disposed between the drain region and the source region and having a second conductivity type opposite to the first conductivity type. The device further includes a plurality of doped regions disposed within the well region. The doped regions are vertically and horizontally offset from each other. Each of the doped regions includes a lower portion having the first conductivity type, and an upper portion stacked on the lower region and having the second conductivity type.

Abstract: A semiconductor device is provided. The device includes a substrate having a first conductivity type. The device further includes a drain region, a source region, and a well region disposed in the substrate. The well region is disposed between the drain region and the source region and having a second conductivity type opposite to the first conductivity type. The device further includes a plurality of doped regions disposed within the well region. The doped regions are vertically and horizontally offset from each other. Each of the doped regions includes a lower portion having the first conductivity type, and an upper portion stacked on the lower region and having the second conductivity type.

Abstract: A semiconductor device including a substrate having an isolation structure therein is disclosed. A capacitor is disposed on the isolation structure and includes a polysilicon electrode, an insulating layer disposed on the polysilicon electrode, and a metal electrode disposed on the insulating layer. A method for forming the semiconductor device is also disclosed.

Abstract: A semiconductor device includes: a plurality of stacked semiconductor layers; a plurality of composite doped regions separately and parallelly disposed in a portion of the semiconductor layers along a first direction; a gate structure disposed over a portion of the semiconductor layers along a second direction, wherein the gate structure covers a portion of the composite doped regions; a first doped region formed in the most top semiconductor layer along the second direction and being adjacent to a first side of the gate structure; and a second doped region formed in the most top semiconductor layer along the second direction and being adjacent to a second side of the gate structure opposite to the first side thereof.