Abstract: “A charge pump used for producing at least a first output voltage and a second output voltage according to an input voltage is disclosed. The charge pump includes a pump unit, first to fourth switches, a first output capacitor and a second output capacitor. During a first period, the input voltage and a first voltage, through a first end and a second end of the pump unit respectively, charge at least an internal capacitor. During a second period, the internal capacitor, based on a second voltage level of the first switch and through the second switch, provides the first output capacitor with charges for producing the first output voltage. Finally, during a third period, the internal capacitor, based on a third voltage level of the third switch and through the fourth switch, provides the second output capacitor with charges for producing the second output voltage.

Abstract: A charge pump for generating an arbitrary voltage level includes “M” pieces of pump units PUi and “M+1” pieces of first switches Sj. The pump unit PUi includes a first terminal Ni,1 coupled to a reference voltage Vi,1, a second terminal Ni,2 coupled to a reference voltage Vi,2, a third terminal Ni,3, a fourth terminal Ni,4 and at least one capacitor Ci. Ci is charged by Vi,1 and Vi,2 during a first period, and a voltage is provided from Ni,4 by Ci according to a voltage at Ni,3 during a second period. The first switch Sj is adapted for electrically connecting the first terminal and the second terminal during the second period. The first and second terminals of Sk is coupled to Nk?1,4 and Nk,3, respectively. The first terminal of S1 receives the input voltage and the second terminal of SM+1 outputs the output voltage.

Abstract: A source driver for driving an M-bit liquid crystal display panel includes a reference voltage generator, 2M-X voltage buffers and a voltage-dividing circuit. The 2M-X voltage buffers are coupled to the reference voltage generator for enhancing the driving abilities of 2M-X reference voltages generated by the reference voltage generator, thereby generating corresponding 2M-X output voltages. The voltage-dividing circuit is coupled to the 2M-X voltage buffers for voltage-dividing the 2M-X output voltages generated by the 2M-X voltage buffers, thereby generating 2M reference voltages required for driving the M-bit liquid crystal display panel.

Abstract: A sample-and-hold device including first and second capacitors, first and second switches, amplifier and feedback network is provided. The amplifier includes first and second input stages, output stage and switchable bias current source. The first switch and the first capacitor are coupled in series between input signal and first voltage, and a common node is coupled to a first positive input terminal of the amplifier. The first switch is on during first period and off during second period. The second switch and the second capacitor are coupled in series between the input signal and second voltage, and a common node is coupled to a second positive input terminal of the amplifier. The second switch is on during second period and off during first period. The switchable bias current source biases the second input stage during first period, and switches to bias the first input stage during second period.

Abstract: A digital data driver including a receiving unit and a digital-to-analog (D/A) converting unit is provided. The D/A converting unit is used to convert N digital data outputted from the receiving unit into corresponding N analog data. The D/A converting unit includes a grey-level voltage generator and K sub D/A converting units. The grey-level voltage generator provides 2M grey-level voltages. The ith sub D/A converting unit includes 2M buffers and N K ? D / A converters. In which, each buffer receives and outputs a corresponding grey-level voltage. The jth D/A converter receives the [ ( i - 1 ) × N K + j ] th digital data, and selects and outputs one of the grey-level voltages that passed the buffers as the [ ( i - 1 ) × N K + j ] th analog data according to the [ ( i - 1 ) × N K + j ] th digital data, where N, K, N K , i and j are the positive integers, 1 ? i ? K ? ? and ? ? 1 ? j ? N K .

Abstract: A method for reducing phase lock time and jittering and a phase lock loop (PLL) using the same adapted for PLL including a charge pump (CP) which includes a pull-up and a pull-down networks used for controlling output voltage of the CP. The output voltage is used for controlling frequency and phase of an output signal of the PLL. The method includes: receiving a reference and a feedback signals; setting the driving capabilities of the pull-up and the pull-down networks to a first driving capability when the phase difference between the reference and the feedback signals is greater than a predetermined value; setting the driving capabilities of the pull-up and the pull-down networks to a second driving capability when the phase difference between the reference and the feedback signals is smaller than the predetermined value, wherein the first driving capability is greater than the second driving capability.

Abstract: An apparatus for driving display panel and a digital-to-analog converter (DAC) thereof are provided. The (M+L)-bit digital data provided by the timing controller is converted into N-channel analog output voltages to control and drive the display panel. The number of the analog voltage lines and the number of the selection switches of the (M+L)-bit DAC in the apparatus for driving display panel can be greatly reduced according to the present invention. Compared to the conventional technology, the chip area of the apparatus for driving display panel is reduced and the cost is thus minimized.

Abstract: An apparatus for driving display panel and a digital-to-analog converter (DAC) thereof are provided. The (M+L)-bit digital data provided by the timing controller is converted into N-channel analog output voltages to control and drive the display panel. The number of the analog voltage lines and the number of the selection switches of the (M+L)-bit DAC in the apparatus for driving display panel can be greatly reduced according to the present invention. Compared to the conventional technology, the chip area of the apparatus for driving display panel is reduced and the cost is thus minimized.

Abstract: A digital-to-analog (D/A) conversion device including a data-latch unit, a D/A conversion unit and a gain amplifier is provided. Wherein, the amplitude of the supply voltages for the reference voltage of the D/A conversion unit is not greater than that of the data-latch unit so that the switches in a switch control unit of the D/A conversion unit can be fully turned on or off without using level-shift units. The output amplifier must have a gain to amplify the output signal of the D/A conversion unit to an expected voltage range.

Abstract: A charge pump control circuit and a control method for controlling charge pumps are disclosed. The output terminal of the charge pump is coupled to a load circuit. The charge pump control circuit includes a detecting and controlling circuit and a controlled oscillator. The detecting and controlling circuit is used to detect the load status of the load circuit and output a control signal according to the load status. The controlled oscillator receives the control signal and outputs at least one clock signal. According to the control signal to control a frequency of the clock signal, the charge pump control circuit controls the charge pump.

Abstract: A method and an apparatus for stabilizing output from a Phase Lock Loop (PLL) and the PLL thereof is disclosed. The method mainly relates to enabling the control voltage of a voltage control oscillator VCO in the PLL remained unchanged by means of turning off a charge-discharge current source of a charge pump in a PLL in response to a detected reference signal lower than a default value. Furthermore, the method enables the pulse frequency output from the VCO no exceeding a default tolerant frequency range in a distance from a desired output frequency. Thus, when the reference signal resumes the original frequency, the PLL can quickly lock the phase and the frequency again.

Abstract: A sample-and-hold device including first and second capacitors, first and second switches, amplifier and feedback network is provided. The amplifier includes first and second input stages, output stage and switchable bias current source. The first switch and the first capacitor are coupled in series between input signal and first voltage, and a common node is coupled to a first positive input terminal of the amplifier. The first switch is on during first period and off during second period. The second switch and the second capacitor are coupled in series between the input signal and second voltage, and a common node is coupled to a second positive input terminal of the amplifier. The second switch is on during second period and off during first period. The switchable bias current source biases the second input stage during first period, and switches to bias the first input stage during second period.

Abstract: A charge pump for generating an arbitrary voltage level includes “M” pieces of pump units PUi and “M+1” pieces of first switches Sj. The pump unit PUi includes a first terminal Ni,1 coupled to a reference voltage Vi,1, a second terminal Ni,2 coupled to a reference voltage Vi,2, a third terminal Ni,3, a fourth terminal Ni,4 and at least one capacitor Ci. Ci is charged by Vi,1 and Vi,2 during a first period, and a voltage is provided from Ni,4 by Ci according to a voltage at Ni,3 during a second period. The first switch Sj is adapted for electrically connecting the first terminal and the second terminal during the second period. The first and second terminals of Sk is coupled to Nk?1,4 and Nk,3, respectively. The first terminal of Si receives the input voltage and the second terminal of SM+1 outputs the output voltage.

Abstract: A charge pump used for producing at least a first output voltage and a second output voltage according to an input voltage is disclosed. The charge pump includes a pump unit, the first to fourth switches, a first output capacitor and a second output capacitor. During a first period, the input voltage and the first voltage, through the first end and the second end of the pump unit respectively, charge at least an internal capacitor. During a second period, the internal capacitor, based on the second voltage level of the first switch and though the second switch, provides the first output capacitor with charges for producing the first output voltage. Finally, during the third period, the internal capacitor, based on the third voltage level of the third switch and though the fourth switch, provides the second output capacitor with charges for producing the second output voltage.

Abstract: An electronic switch and an operational method for transistor are provided. The electronic switch includes a switch transistor and a bulk switch. The switch transistor has at least a first terminal, a second terminal and a third terminal. According to the third terminal, the connecting status between the first and the second terminal is determined. The bulk switch is coupled to the bulk of the switch transistor for determining whether to connect the bulk to the first or the second terminal of the switch transistor according to at least one control signal.

Abstract: A sample-and-hold circuit including a first switch, a first capacitor and an amplifier is provided. The switch has a first terminal to receive the input signal and transmit it to a second terminal thereof in the sample period. The first terminal of the first capacitor couples to the second terminal of the first switch, and the second terminal of the first capacitor couples to a first voltage for storing the sampling result of the input signal. The amplifier couples to the second terminal of the first switch, wherein the amplifier is disabled in the sample period, and the amplifier is enabled to generate the output signal according to the sampling result in the hold period.

Abstract: A method for enhancing efficiency of charge pump circuit, and a charge pump control selector are provided. Power consumption of output, delivered from the charge pump unit to the load circuit, is detected. A sample signal is obtained and compared with a reference signal to generate a comparison signal. The comparison signal is converted to a control signal to provide feedback for tuning the input frequency of the charge pump unit. The detection of load is categorized in two detection modes, the voltage detection mode, and the current detection mode. The detection modes detect variations of ripple amplitudes of the output voltage of the charge pump circuit and variations of the load currents. The comparator converts the sample signal to a comparison signal. According to the comparison signal, the control method of the controller is determined. The controllers are categorized as continuous controller and discontinuous controller.

Abstract: A voltage-controlled current source (VCCS) is provided. The VCCS controls an output current according to a controlling voltage. The VCCS includes an operational amplifier (OP-amplifier), a transistor, a resistor and a current mirror. The present invention utilizes the characteristics of the OP-amplifier to compensate for the voltage difference between the gate and the source of the transistor so that the resulting terminal voltage on the resistor is equal to the input control voltage. Therefore, the VCCS of the present invention can reduce the factors including process drift, fluctuation in the DC voltage source or the output current that can affect the terminal voltage difference of the resistor and hence the accuracy of the output current.