Abstract: An aiming system includes a positioner, an aiming device, and a processor. The positioner has a function of acquiring spatial information, and the aiming device is connected to the positioner, and the processor is connected to the positioner or the aiming device. A method of using the aiming system is also provided. Surgical guidance is more intuitive by directly combining the positioner with the aiming device.

Abstract: A method of correcting a misalignment of a wafer on a wafer holder and an apparatus for performing the same are disclosed. In an embodiment, a semiconductor alignment apparatus includes a wafer stage; a wafer holder over the wafer stage; a first position detector configured to detect an alignment of a wafer over the wafer holder in a first direction; a second position detector configured to detect an alignment of the wafer over the wafer holder in a second direction; and a rotational detector configured to detect a rotational alignment of the wafer over the wafer holder.

Abstract: A fan includes a fan hub and multiple blades. At least one blade includes a blade body and two extended blade portions. The two extended blade portions are connected to a first edge and a second edge on the blade body. The first edge and the second edge are opposite to sides of the blade body. In a top view, at least one of the two extended blade portions has a first width that is adjacent to the fan hub, and a second width that is away from the fan hub. The second width is larger than the first width. The second width and the first width are connected by a continuous surface. The width of the continuous surface increases away from the first width.

Abstract: A method includes coating a photoresist film over a target layer; performing a lithography process to pattern the photoresist film into a photoresist layer, wherein the photoresist layer has an opening, and the opening of the photoresist layer at least has a first sidewall, a second sidewall non-parallel with the first sidewall, and a first corner connecting the first and second sidewalls; performing a first directional ion bombardment process to the first corner of the photoresist layer along a first direction, wherein the first direction is non-perpendicular to both the first and second sidewalls of the photoresist when viewed from top; and after the first directional ion bombardment process is complete, patterning the target layer using the photoresist layer as a patterning mask.

Abstract: A heat dissipating system for electronic devices includes a first heat dissipation device, a second heat dissipation device, and a thermal conduction component. The thermal conduction component is disposed around the first heat dissipation device and configured to thermally contact a heat source. The second heat dissipation device is disposed adjacent to the thermal conduction component. The first heat dissipation device is configured to generate a first working fluid toward the thermal conduction component, such that the heat transferred from the heat source to the thermal conduction component is dispersed in a plurality of directions directing away from the first heat dissipation device. The second heat dissipation device is configured to generate a second working fluid, such that the heat distributed adjacent to the second heat dissipation device is dissipated in at least one direction directing away from the second heat dissipation device.

Abstract: A method of correcting a misalignment of a wafer on a wafer holder and an apparatus for performing the same are disclosed. In an embodiment, a semiconductor alignment apparatus includes a wafer stage; a wafer holder over the wafer stage; a first position detector configured to detect an alignment of a wafer over the wafer holder in a first direction; a second position detector configured to detect an alignment of the wafer over the wafer holder in a second direction; and a rotational detector configured to detect a rotational alignment of the wafer over the wafer holder.

Abstract: A method for forming a semiconductor device is provided. In some embodiments, the method includes forming a target layer over a semiconductor substrate, forming a carbon-rich hard masking layer over the target layer, patterning features in the carbon-rich hard masking layer using an etching process, performing a directional ion beam trimming process on the features patterned in the carbon-rich hard masking layer, and patterning the target layer using the carbon-rich hard masking layer as a mask.

Abstract: A heat dissipating system for electronic devices includes a first heat dissipation device, a second heat dissipation device, and a thermal conduction component. The thermal conduction component is disposed around the first heat dissipation device and configured to thermally contact a heat source. The second heat dissipation device is disposed adjacent to the thermal conduction component. The first heat dissipation device is configured to generate a first working fluid toward the thermal conduction component, such that the heat transferred from the heat source to the thermal conduction component is dispersed in a plurality of directions directing away from the first heat dissipation device. The second heat dissipation device is configured to generate a second working fluid, such that the heat distributed adjacent to the second heat dissipation device is dissipated in at least one direction directing away from the second heat dissipation device.

Abstract: An air cooling system for electronic devices includes a body, a thermal conduction component, and a heat dissipation fan. The body has a heat dissipation port and air inlet ports. The air inlet ports are disposed at a first housing part and a second housing part of the body. The first housing part is opposite to the second housing part. The thermal conduction component is disposed in the body and configured to contact a heat source. The heat dissipation fan is disposed in the body. The heat dissipation fan includes a first axial air inlet opening, a second axial air inlet opening, and radial air outlet openings. The first axial air inlet opening corresponds to one of the air inlet ports of the first housing part. The second axial air inlet opening corresponds to one of the air inlet ports of the second housing part.

Abstract: A semiconductor process system includes an ion source configured to bombard with a photoresist structure on a wafer. The semiconductor process system reduces a width of the photoresist structure by bombarding the photoresist structure with ions in multiple distinct ion bombardment steps having different characteristics.

Abstract: A connector assembly for mounting a chip module to a printed circuit board (PCB) includes: a seating mechanism including a socket connector, a metallic seat frame, and a metallic load plate; a back plate; and plural fasteners extending through the seating mechanism, the PCB, and the back plate to fasten the seating mechanism and the back plate on two opposite sides of the PCB, wherein the back plate has a curved inner region and a flat outer region and the fasteners extend through the flat outer region of the back plate.

Abstract: A method for forming a semiconductor device is provided. In some embodiments, the method includes forming a target layer over a semiconductor substrate, forming a carbon-rich hard masking layer over the target layer, patterning features in the carbon-rich hard masking layer using an etching process, performing a directional ion beam trimming process on the features patterned in the carbon-rich hard masking layer, and patterning the target layer using the carbon-rich hard masking layer as a mask.

Abstract: A three-dimensional memory device and a method of manufacturing a three-dimensional memory device are provided. The method includes providing a precursor structure including a substrate, a multi-layered stack, a plurality of vertical channel pillars and a barrier structure. A first slit and a second slit are then formed in the multi-layered stack and the substrate along a first direction, in which the first slit and the second slit have a pitch between thereof, and the second slit cuts the barrier structure. A portion of the second insulating layers is then replaced with a plurality of conductive layers. A first slit structure and a second slit structure are then formed in the first slit and the second slit, in which the first slit structure and the second slit structure separate the vertical channel pillars in a second direction that is different from the first direction.

Abstract: An embodiment of the present the disclosure provides a memory device, including: a substrate, an interconnection structure disposed on the substrate, a conductive layer disposed on the interconnection structure, a stop layer disposed on the conductive layer, and a gate stack structure disposed on the stop layer. The gate stack structure includes a plurality of insulating layers and a plurality of gate conductive layers that alternate with each other. A ratio of a thickness of a bottommost insulating layer of the gate stack structure to a thickness of the stop layer is 1:1 to 1:2. The memory device further includes a channel pillar extending through the gate stack structure and the stop layer and to electrically connect the conductive layer, and a charge storage structure disposed between sidewalls of the channel pillar and the plurality of gate conductive layers.

Abstract: Apparatus and methods for unknown physical uplink control channel (PUCCH) secondary cell (SCell) activation are proposed. The network node may transmit a PUCCH SCell activation command for an unknown target PUCCH SCell to the UE. After receiving the PUCCH SCell activation command for the unknown target PUCCH SCell, the UE may transmit a layer 1 (L1) report or a layer 3 (L3) report for the unknown target PUCCH SCell to the network node before the unknown target PUCCH SCell is activated. The network node may obtain measurement information based on the L1 report or the L3 report before the unknown target PUCCH SCell is activated. Then, the network node may perform corresponding operations based on the L1 report or the L3 report before the unknown target PUCCH SCell is activated.

Abstract: A method for forming a semiconductor device is provided. In some embodiments, the method includes forming a target layer over a semiconductor substrate, forming a carbon-rich hard masking layer over the target layer, patterning features in the carbon-rich hard masking layer using an etching process, performing a directional ion beam trimming process on the features patterned in the carbon-rich hard masking layer, and patterning the target layer using the carbon-rich hard masking layer as a mask.

Abstract: A method includes patterning a hard mask over a target layer, capturing a low resolution image of the hard mask, and enhancing the low resolution image of the hard mask with a first machine learning model to produce an enhanced image of the hard mask. The method further includes analyzing the enhanced image of the hard mask with a second machine learning model to determine whether the target layer has defects.

Abstract: A critical dimension uniformity control method is provided. The method includes gathering a first CDU by a first critical dimension from a first wafer after being processed by a first surface process. The method includes determining a first calibration process based on the first CDU. The determining includes an intra dose correction step for correcting reticle-dependent deviation, a thru-slit dose sensitivity correction step for correcting time-dependent deviation, and an inter dose correction step for correcting process-dependent deviation. The method includes calibrating the first surface process by the first calibration process to determine a second surface process different from the first surface process.

Abstract: In an embodiment, a method includes: placing a wafer on an implanter platen, the wafer including alignment marks; measuring a position of the wafer by measuring positions of the alignment marks with one or more cameras; determining an angular displacement between the position of the wafer and a reference position of the wafer; and rotating the implanter platen by the angular displacement.

Abstract: A method includes providing a substrate of a first conductivity type, the substrate including a first circuit region and a second circuit region; forming a first well region of a second conductivity type in the first circuit region of the substrate; forming a first doped region of the second conductivity type in the first well region; forming a diode in the second circuit region of the substrate; forming a first transistor and a second transistor over the substrate in the first circuit region and the second circuit region, respectively; forming a discharge structure over the substrate to electrically couple the first doped region to the diode; and forming a metallization layer over the discharge structure to electrically couple the first transistor to the second transistor subsequent to the forming of the diode, wherein charges accumulated in the first well region are drained to the substrate through the discharge structure.