Patents by Inventor Chih-Pin Hung
Chih-Pin Hung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180358238Abstract: The present disclosure relates to a semiconductor device package comprising a substrate, a semiconductor device, and a underfill. The substrate includes a top surface defining a mounting area, and a barrier section on the top surface and adjacent to the mounting area. The semiconductor device is mounted on the mounting area of the substrate. The underfill is disposed between the semiconductor device and the mounting area and the barrier section of the substrate. A contact angle between a surface of the underfill and the barrier section is greater than or equal to about 90 degrees.Type: ApplicationFiled: June 9, 2017Publication date: December 13, 2018Inventors: Jin-Yuan LAI, Tang-Yuan CHEN, Ying-Xu LU, Dao-Long CHEN, Kwang-Lung LIN, Chih-Pin HUNG, Tse-Chuan CHOU, Ming-Hung CHEN, Chi-Hung PAN
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Publication number: 20180226320Abstract: A semiconductor package includes a substrate, a semiconductor chip and a heat dissipation structure. The semiconductor chip includes a first surface, a second surface opposite to the first surface, and at least one chip pad disposed adjacent to the first surface. The chip pad is electrically connected to the substrate. The heat dissipation structure is disposed adjacent to the second surface of the semiconductor chip and a portion of the substrate. An area of the heat dissipation structure is greater than an area of the semiconductor chip.Type: ApplicationFiled: February 9, 2017Publication date: August 9, 2018Inventors: Ian HU, Jia-Rung HO, Jin-Feng YANG, Chih-Pin HUNG, Ping-Feng YANG
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Patent number: 10014250Abstract: A semiconductor device includes a substrate and at least one inductor on the substrate. The inductor includes top portions separated from one another, bottom portions separated from one another, and side portions separated from one other. Each side portion extends between one of the top portions and one of the bottom portions. A semiconductor device includes a substrate, a first patterned conductive layer on the substrate, a second patterned conductive layer, and at least one dielectric layer between the first patterned conductive layer and the second patterned conductive layer. The first patterned conductive layer defines bottom crossbars separated from each other, each bottom crossbar including a bend angle. The second patterned conductive layer defines top crossbars separated from each other, wherein each top crossbar is electrically connected to a bottom crossbar.Type: GrantFiled: February 9, 2016Date of Patent: July 3, 2018Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Sheng-Chi Hsieh, Chih-Pin Hung
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Publication number: 20180158766Abstract: A method of manufacturing a semiconductor package includes: (a) providing a carrier; (b) disposing a dielectric layer and a conductive pad on the carrier; (c) disposing a redistribution layer on the dielectric layer to electrically connect to the conductive pad; (d) connecting a die to the redistribution layer; (e) removing at least a portion of the carrier to expose the conductive pad; and (f) disposing an electrical contact to electrically connect to the conductive pad.Type: ApplicationFiled: January 30, 2018Publication date: June 7, 2018Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chien Lin CHANG CHIEN, Chin-Li KAO, Chang Chi LEE, Chih-Pin HUNG
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Patent number: 9917071Abstract: A semiconductor package includes: a first substrate including a first interconnection structure extending from a surface of the first substrate, the first interconnection structure including grains of a first size, a second substrate including: a second interconnection structure comprising grains of a second size, and a third interconnection structure disposed between the first interconnection structure and the second interconnection structure, the third interconnection structure including grains of a third size, a first sidewall inclined at a first angle to a reference plane and a second sidewall inclined at a second angle to the reference plane, wherein the first angle is different from the second angle, the first sidewall is disposed between the first substrate and the second sidewall, and the third size is smaller than both the first size and the second size.Type: GrantFiled: December 7, 2016Date of Patent: March 13, 2018Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Ying-Ta Chiu, Yong-Da Chiu, Dao-Long Chen, Chih-Cheng Lee, Chih-Pin Hung
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Patent number: 9917043Abstract: In one or more embodiments, a semiconductor package includes a redistribution layer, a conductive pad, a dielectric layer, a silicon layer, and a conductive contact. The redistribution layer includes a first surface and a second surface opposite to the first surface. The conductive pad is on the first surface of the redistribution layer. The dielectric layer is disposed on the first surface of the redistribution layer to cover a first portion of the conductive pad and to expose a second portion of the conductive pad. The silicon layer is disposed on the dielectric layer, the silicon layer having a recess to expose the second portion of the conductive pad. The conductive contact is disposed over the silicon layer and extends into the recess of the silicon layer.Type: GrantFiled: April 4, 2017Date of Patent: March 13, 2018Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chien Lin Chang Chien, Chin-Li Kao, Chang Chi Lee, Chih-Pin Hung
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SEMICONDUCTOR DEVICE PACKAGES AND STACKED PACKAGE ASSEMBLIES INCLUDING HIGH DENSITY INTERCONNECTIONS
Publication number: 20180047571Abstract: A semiconductor device package includes an electronic device and a redistribution stack. The redistribution stack includes a dielectric layer disposed over an active surface of the electronic device and defining an opening exposing at least a portion of a contact pad of the electronic device. The redistribution stack also includes a redistribution layer disposed over the dielectric layer and including a trace. A first portion of the trace extends over the dielectric layer along a longitudinal direction adjacent to the opening, and a second portion of the trace is disposed in the opening and extends between the first portion of the trace and the exposed portion of the contact pad. The second portion of the trace has a maximum width along a transverse direction orthogonal to the longitudinal direction, and the maximum width of the second portion of the trace is no greater than about 3 times of a width of the first portion of the trace.Type: ApplicationFiled: June 6, 2017Publication date: February 15, 2018Inventors: John Richard HUNT, William T. Chen, Chih-Pin HUNG, Chen-Chao WANG -
Publication number: 20170365515Abstract: The present disclosure relates to a semiconductor package structure and a method of manufacturing the same. The semiconductor package structure includes a semiconductor substrate having a first surface and a second surface opposite the first surface. The semiconductor substrate has a space extending from the second surface to the first surface and an insulation body is disposed in the space. The semiconductor package structure includes conductive posts in the insulation body.Type: ApplicationFiled: June 16, 2016Publication date: December 21, 2017Inventors: Chin-Cheng KUO, Pao-Nan LEE, Chih-Pin HUNG, Ying-Te OU
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Publication number: 20170278814Abstract: A semiconductor device includes a semiconductor element, a trace disposed adjacent to a surface of the semiconductor element, a bonding pad disposed adjacent to the surface of the semiconductor element and connected to the trace, and a pillar disposed on the bonding pad. The pillar includes a first end wall, a second end wall opposite the first end wall, a first side wall, and a second side wall opposite the first side wall. The first side wall and the second side wall connect the first end wall to the second end wall. One or both of the first side wall and the second side wall incline inwardly from the first end wall to the second end wall. The pillar is disposed on the bonding pad such that the first end wall is closer to the trace than is the second end wall.Type: ApplicationFiled: March 22, 2016Publication date: September 28, 2017Inventors: Chih-Pin HUNG, Dao-Long CHEN, Ying-Ta CHIU, Ping-Feng YANG
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Publication number: 20170229393Abstract: A semiconductor device includes a substrate and at least one inductor on the substrate. The inductor includes top portions separated from one another, bottom portions separated from one another, and side portions separated from one other. Each side portion extends between one of the top portions and one of the bottom portions. A semiconductor device includes a substrate, a first patterned conductive layer on the substrate, a second patterned conductive layer, and at least one dielectric layer between the first patterned conductive layer and the second patterned conductive layer. The first patterned conductive layer defines bottom crossbars separated from each other, each bottom crossbar including a bend angle. The second patterned conductive layer defines top crossbars separated from each other, wherein each top crossbar is electrically connected to a bottom crossbar.Type: ApplicationFiled: February 9, 2016Publication date: August 10, 2017Inventors: Sheng-Chi HSIEH, Chih-Pin HUNG
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Publication number: 20170207153Abstract: In one or more embodiments, a semiconductor package includes a redistribution layer, a conductive pad, a dielectric layer, a silicon layer, and a conductive contact. The redistribution layer includes a first surface and a second surface opposite to the first surface. The conductive pad is on the first surface of the redistribution layer. The dielectric layer is disposed on the first surface of the redistribution layer to cover a first portion of the conductive pad and to expose a second portion of the conductive pad. The silicon layer is disposed on the dielectric layer, the silicon layer having a recess to expose the second portion of the conductive pad. The conductive contact is disposed over the silicon layer and extends into the recess of the silicon layer.Type: ApplicationFiled: April 4, 2017Publication date: July 20, 2017Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chien Lin CHANG CHIEN, Chin-Li KAO, Chang Chi LEE, Chih-Pin HUNG
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Publication number: 20170200702Abstract: In one or more embodiments, a semiconductor device includes a substrate, a first dielectric layer and a first conductive layer. The substrate includes a first surface and a second surface opposite the first surface. The first dielectric layer is on the first surface of the substrate. The first conductive layer is on the first surface of the substrate and includes a first portion on the first dielectric layer and a second portion surrounded by the first dielectric layer. The second portion of the first conductive layer extends from the first portion of the first conductive layer through the first dielectric layer to contact the first surface of the substrate.Type: ApplicationFiled: January 11, 2017Publication date: July 13, 2017Inventors: Chih-Pin HUNG, Ying-Te OU, Pao-Nan LEE
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Patent number: 8653633Abstract: Described herein are semiconductor device packages with EMI shielding and related methods. In one embodiment, a semiconductor device package includes: (1) a substrate unit including a grounding element; (2) a semiconductor device disposed adjacent to an upper surface of the substrate unit; (3) a package body disposed adjacent to the upper surface of the substrate unit and covering the semiconductor device; and (4) an EMI shield disposed adjacent to exterior surfaces of the package body and electrically connected to a connection surface of the grounding element. A lateral surface of the package body is substantially aligned with a lateral surface of the substrate unit, and the connection surface of the grounding element is electrically exposed adjacent to the lateral surface of the substrate unit. The grounding element corresponds to a remnant of an internal grounding via, and provides an electrical pathway to ground electromagnetic emissions incident upon the EMI shield.Type: GrantFiled: July 5, 2011Date of Patent: February 18, 2014Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Kuo-Hsien Liao, Chi-Tsung Chiu, Chih-Pin Hung
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Publication number: 20130150991Abstract: The invention relates to a data processing module of a digital audio processing device, a digital audio processing controller module of a portable device and a control system. Using the data processing module of the digital audio processing device and the digital audio processing controller module of the portable device, the portable device can transmit control command packet to control the digital audio processing device. The user can use a large-size screen of the portable device to control the digital audio processing device to overcome the shortage in the display function of conventional device. Furthermore, when using the portable device under the condition where the hardware of the digital audio processing device is not changed, the functions of the digital audio processing device can be additionally extended. Therefore, the extended functions of the digital audio processing device can be flexibly added in response to customers and DJ's requirements.Type: ApplicationFiled: April 9, 2012Publication date: June 13, 2013Applicant: HANPIN ELECTRON CO., LTD.Inventors: SHEN-CHI LIU, TES-MING LAN, SHENG-FENG WENG, CHIH-PIN HUNG
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Patent number: 8350367Abstract: Described herein are semiconductor device packages with EMI shielding and related methods. In one embodiment, a semiconductor device package includes: (1) a substrate unit including a grounding element disposed adjacent to a periphery of the substrate unit; (2) a semiconductor device disposed adjacent to an upper surface of the substrate unit; (3) a package body disposed adjacent to the upper surface and covering the semiconductor device; and (4) an EMI shield disposed adjacent to exterior surfaces of the package body and electrically connected to a connection surface of the grounding element. A lateral surface of the package body is substantially aligned with a lateral surface of the substrate unit, and the connection surface of the grounding element is electrically exposed adjacent to the lateral surface of the substrate unit. The grounding element corresponds to a remnant of a grounding via, and provides an electrical pathway to ground electromagnetic emissions incident upon the EMI shield.Type: GrantFiled: December 16, 2008Date of Patent: January 8, 2013Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Chi-Tsung Chiu, Chih-Pin Hung, Jui-Cheng Huang
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Patent number: 8212339Abstract: Described herein are semiconductor device packages with EMI shielding and related methods. In one embodiment, a semiconductor device package includes a grounding element disposed adjacent to a periphery of a substrate unit and at least partially extending between an upper surface and a lower surface of the substrate unit. The grounding element includes an indented portion that is disposed adjacent to a lateral surface of the substrate unit. The semiconductor device package also includes an EMI shield that is electrically connected to the grounding element and is inwardly recessed adjacent to the indented portion of the grounding element.Type: GrantFiled: April 29, 2010Date of Patent: July 3, 2012Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Kuo-Hsien Liao, Jian-Cheng Chen, Chen-Chuan Fan, Chi-Tsung Chiu, Chih-Pin Hung
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Publication number: 20110260301Abstract: Described herein are semiconductor device packages with EMI shielding and related methods. In one embodiment, a semiconductor device package includes: (1) a substrate unit including a grounding element; (2) a semiconductor device disposed adjacent to an upper surface of the substrate unit; (3) a package body disposed adjacent to the upper surface of the substrate unit and covering the semiconductor device; and (4) an EMI shield disposed adjacent to exterior surfaces of the package body and electrically connected to a connection surface of the grounding element. A lateral surface of the package body is substantially aligned with a lateral surface of the substrate unit, and the connection surface of the grounding element is electrically exposed adjacent to the lateral surface of the substrate unit. The grounding element corresponds to a remnant of an internal grounding via, and provides an electrical pathway to ground electromagnetic emissions incident upon the EMI shield.Type: ApplicationFiled: July 5, 2011Publication date: October 27, 2011Inventors: Kuo-Hsien Liao, Chi-Tsung Chiu, Chih-Pin Hung
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Patent number: 8022511Abstract: Described herein are semiconductor device packages with EMI shielding and related methods. In one embodiment, a semiconductor device package includes: (1) a substrate unit; (2) a grounding element disposed adjacent to a periphery of the substrate unit and extending upwardly from an upper surface of the substrate unit; (3) a semiconductor device disposed adjacent to the upper surface; (4) a package body disposed adjacent to the upper surface and covering the semiconductor device and the grounding element; and (5) an EMI shield disposed adjacent to exterior surfaces of the package body and electrically connected to a lateral surface of the grounding element. A lateral surface of the package body is substantially aligned with a lateral surface of the substrate unit. The grounding element corresponds to a remnant of a conductive bump, and provides an electrical pathway to ground electromagnetic emissions incident upon the EMI shield.Type: GrantFiled: December 16, 2008Date of Patent: September 20, 2011Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Chi-Tsung Chiu, Chih-Pin Hung, Jui-Cheng Huang
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Patent number: 8000107Abstract: A carrier with embedded components comprises a substrate and at least one embedded component. The substrate has at least one slot and a first composite layer. The embedded component is disposed at the slot of the substrate. The first composite layer has a degassing structure, at least one first through hole and at least one first fastener, wherein the degassing structure corresponds to the slot, the first through hole exposes the embedded component, and the first fastener is formed at the first through hole and contacts the embedded component. According to the present invention, the degassing structure can smoothly discharge the hydrosphere existing within the carrier under high temperature circumstances and the first fastener is in contact with the embedded component, which increases the joint strength between the embedded component and the substrate.Type: GrantFiled: March 28, 2008Date of Patent: August 16, 2011Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Yung-Hui Wang, In-De Ou, Chih-Pin Hung
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Patent number: 7989928Abstract: Described herein are semiconductor device packages with EMI shielding and related methods. In one embodiment, a semiconductor device package includes: (1) a substrate unit including a grounding element; (2) a semiconductor device disposed adjacent to an upper surface of the substrate unit; (3) a package body disposed adjacent to the upper surface of the substrate unit and covering the semiconductor device; and (4) an EMI shield disposed adjacent to exterior surfaces of the package body and electrically connected to a connection surface of the grounding element. A lateral surface of the package body is substantially aligned with a lateral surface of the substrate unit, and the connection surface of the grounding element is electrically exposed adjacent to the lateral surface of the substrate unit. The grounding element corresponds to a remnant of an internal grounding via, and provides an electrical pathway to ground electromagnetic emissions incident upon the EMI shield.Type: GrantFiled: June 22, 2009Date of Patent: August 2, 2011Assignee: Advanced Semiconductor Engineering Inc.Inventors: Kuo-Hsien Liao, Chi-Tsung Chiu, Chih-Pin Hung