Abstract: A method of compressing an image by referring to the correlation of previous line information results in high image quality. A register is used to save the previous line information and the derived predictive method for compressing future line of pixels. Another register is used to save the complexity of the previous line for more accurately calculating the bit rate distribution of each segment for compressing future line.

Abstract: This invention provides efficient method and apparatus of the motion estimation for the video compression. A storage device saving MVs of a partial or an entire frame and the prediction modes are applied to be the reference for the motion estimation of the neighboring frame. The majority MV of the current frame and at least one neighboring frame is referred as the MV or as the initial point of searching for the current frame or the neighboring frames. Should the movement of the blocks in previous frame is different from the FMV, will the blocks or the neighboring blocks need to go through the motion estimation. The predetermined threshold values are specified to decide the need of a refiner pixel resolution, the sub-sampling ratio, and early giving up or early selecting of the current macroblock. Sub-sampling ratio or the decision of refiner or coarser pixel resolution is determined by the values of the MV or MAD.

Abstract: An image compression method and fast storage device accessing and pixel decompression is achieved by applying variable bit rate to reduce the data amount of each image frame. Several thresholds are predetermined depending on the availability of the bandwidth of the storage device and the image resolution to decide the compression ratio of each image frame. Starting address of each compressed image frame is saved in predetermined location of the storage device for quick random accessing any compressed frame of image.

Abstract: The present invention provides a sensing scheme for semiconductor memory. N-type devices coupling between ground and a bit line and a bit line-bar of memory cells quickly discharge a bit line and a bit line-bar during non-accessing mode. During data accessing mode, one P-type device of an SRAM memory cell pulls up bit line or bit line-bar node slowly to minimize the inductive coupling noise and VDD, Ground bouncing, hence allows smaller amount of differential voltage input to the sense amplifier and results in lower power consumption. A self-timer counts the needed time and sends a signal to enable the current driven sense amplifier and to turn off the word line to avoid further pulling up the bit line or bit line-bar voltage and to reduce the power dissipation.

Abstract: Compression and decompression with high image quality is applied to reduce the data rate of transmitting an image results in high efficiency image transmission between TV and display device is presented. An LVDS bus is hooked between the TV side and display device with this invention of image compression apparatus in the TV side to reduce data rate and image decompression in the display device to reconstruct the image to be displayed.

Abstract: This image compression applies a mixture compression algorithm to code the differential value of the adjacent pixels. The first table saves a predetermined number of the most frequent patterns and the second table saves another predetermined number of the most frequent patterns and both apply fixed length code to represent the matched pattern of current pixel.

Abstract: An image compression method for compressing groups of pixel data, including the following steps: MSB portions and LSB portions of the pixel data are compressed separately. Further, the LSB portions are grouped according to their associated MSB portions so that similar pixels are compressed together to gain higher a compression ratio. Some LSB portions are truncated to ensure a compression ratio. When performing compression, enhanced variable-length coding is adopted that predicts more accurate dividers by considering weighted combination of adjacent pixels. The quotient of each groups of compression portion is predicted and coded accordingly.

Abstract: Inter-frame and intra-frame block pixel compression means are applied to re-compress the decompressed video field/frame for future digital video decompression, de-interlacing and frame conversion. The motion vectors, MVs, decompressed from the compressed video field/frame are temporarily saved in a buffer for future inter-frame coding of block by block re-compression. If the input video frames are uncompressed or decompressed fields/frames, they will be compressed before saving into an off-chip frame buffer, later, the accessed lines of compressed pixels of at least two fields/frames will be used for de-interlacing and frame rate conversion. If the corresponding MV is out of the predetermined threshold, inter-frame coding will be skipped and only intra-frame coding is applied.

Abstract: The digital video encoder or video decoder with referencing frame image compression and decompression mechanism allows a smaller on-chip referencing frame storage device and efficient off-chip referencing frame random access. In using the off-chip frame buffer, a predetermined amount of line buffer temporarily saves the compressed pixels and reconstructs the needed macro-block pixels according to the motion vector for motion compensation in video decoder and reconstructs the searching range pixels for motion estimation in video encoder.

Abstract: The digital video decompression, de-interlacing and frame conversion are done simultaneously with multiple video decompressing engines decoding multiple fields/frames at a time. The on-chip line buffer temporarily stores multiple rows of macro-block pixels of the video decoding referencing field/frame and the reconstructed field/frame and are used simultaneously in de-interlacing and frame rate conversion.

Abstract: The present invention provides a new semiconductor Random Access Memory, RAM which stores multiple bits per cell. When writing data, at least three levels of voltage sources are generated to charge the bit line and the RAM capacitive device through the selective devices. During reading data, at least three referencing voltage sources are input to at least three sense amplifiers to differentiate at least four levels of bit line voltages and convert the differential levels to at least two logic bits.

Abstract: An image frame is compressed segment by segment by applying a lossless compression algorithm to the segment of pixels with simple pattern and a lossy algorithm to the segment with complex pattern. A segment comprising at least one homogenous area and one complex area will be compressed separately by assigning a lossless compression algorithm to compress the homogenous area and a lossly algorithm to compress the complex area. Another mechanism of partitioning a segment into multiple sub-segments with each sub-segment being compressed by one compression algorithm also helps in reducing the error in the homogenous area.

Abstract: The digital video referencing frame image is compressed block by block by applying lossless compression algorithm to pixel components with full length, or 1 bit, 2 bits, 3 bits or 4 bits LSB bits truncation. If a sub-block has high complexity which results in more than 3 bits error for most pixel components, a transfer algorithm with quantization and VLC coding is applied to compress this sub-block. Should the complexity is higher than a threshold or at least one sub-block having error of more than 3 bits for most pixel components, truncating 1 LSB bit of sub-block with simple pattern to save more bits to be allocate to code the sub-block with highest complex pattern.

Abstract: The digital video referencing frame image is compressed block by block with each block having a predetermined data rate and each block pixels are divided to be multiple sub-blocks with each sub-block having its divider to code the quotient and remainder of the differential values of adjacent pixel components. A group of blocks pixels share the same referencing pixel component with each block contributes one referencing pixel component and 2 bits to identify the block of most complex pattern falls on. A predetermined data rate is assigned to represent the first pixel component and another predetermined data rate is assigned to represent the first pixel component of a block. An extra amount of bits to represent either the first pixel component or the second and the third pixel components is allowed.

Abstract: The differential value of the adjacent pixels is calculated firstly and is coded by a VLC coding. The VLC coding includes codes representing the Quotient and Remainder with a marker bit inserted in between. The divider is predicted with no code in the coded data stream. If three pixel components are presented in the same clock time, three VLC encoders and three VLD decoders are applied to encode and decode one pixel at a time. During encoding, both Remainder and Quotient of the same pixel component are encoded in parallel followed. During decoding, both Remainder and Quotient of the same pixel component are decoded in parallel and the results of the first pixel component are used a reference to decode the second pixel component which adopts the same decoding procedure and the decoded results of the second pixel component is used as reference to decode the third pixel component.

Abstract: A compression method and apparatus compresses the instruction for a CPU which significantly reduces the density of storage device of storing the program. Multiple groups of instructions are compressed separately by a mapping unit indicating the starting location of a group of instructions which helps quickly recovering the corresponding instructions. In decoding, multiple instructions are decoded in parallel to quickly recover instructions to avoid running out of instruction in the file register. A mapping unit is used to translate the corresponding address of a group of data for quickly recovering the corresponding data for the file register file to avoid running out of data for a CPU to execute.

Abstract: An image compression method and fast storage device accessing and pixel decompression is achieved by asserting the starting location of one or more groups of compress pixels. Information of at least one upper line of pixel's pattern complexity is temporarily saved into a register for predicting the code length of the targeted pixel of the current line and deciding the coding method.

Abstract: The captured video will be compressed group by group and transmitted to the receiver through wireless transceiver. The mechanism of the wireless video communication includes the defining of whether or not to request resend when data loss or data damage happened. When the time of the data loss or data damage happened is more than the predetermined threshold, the video will be compressed by further lower bit rate. Areas of the captured image with more interest will be compressed by assigning more bit rate. The area of less interest will be compressed with less bit rate and transmitted. One of every predetermined amount of images will be shrunk and displayed in the smaller area of the display device to let the video shooter view the position the image is captured and decides whether the position results in good image quality.

Abstract: A device of decompressing video data, scaling the image and displaying to a displaying device significantly reduces the power consumption. The compressed video data is reconstructed and temporarily compressed before storing into a temporary display frame buffer and decompressed before displaying in a display device. A video data is partially decoded to the DCT domain and scaled according to the resolution of display before the video decompression. A video communication device includes an image sensor integrated together with the video compression engine into the same die and a display driver with the video decompression engine integrated together in the same die.

Abstract: The present invention provides a new semiconductor Read-Only Memory, ROM, which stores more than one bit per cell. The potential of multiple threshold voltages combined with the potential multiple ratios of device channel width and length makes an ROM cell store multiple bits feasible. An N-type or a P-type MOS device of the standard CMOS process or a flat-cell mask ROM process are operable devices and processes in the design of this multi layer cell ROM. The ROM cell with smaller size is implemented to represent the LSB bits, while the larger size ROM cell is to represent the MSB bits.