Abstract: The present invention provides method and apparatus of a lossless data compression to reduce the amount of data to be transmitted or to be saved into a storage device. In the VLSI implementation, a data path module combined with some state machines support multiple formats of data file and to execute the function of the lossless data compression. The amount of the program data of a File System is reduced by a lossless compression method before it is saved into the storage device and to be recovered to execute the function of a File System. Before transmission, the data file compressed by the lossless compression algorithm coupled with the corresponding decompression code will be packed into a data stream and the receiving node will recover the data file by executing the decompression code.

Abstract: The present invention provides method and apparatus of image buffer compression for video bit stream encoding. At least one re-constructed referencing frame pixel is compressed again and stored in a storage device. During motion estimation of a video compression, a decompressing engine recovered pixels of the predetermined searching range for best match block searching. In the still image compression, a lossless compression algorithm is applied to compress pixel data of at least one line of pixels and to save the compressed pixels into a storage device, decompression mechanism recovers at least one pixel of at least one line of pixels for predicting the value of a target pixel.

Abstract: The present invention provides a sensing scheme for semiconductor memory. N-type devices coupling between ground and a bit line and a bit line-bar of memory cells quickly discharge a bit line and a bit line-bar during non-accessing mode. During data accessing mode, one P-type device of an SRAM memory cell pulls up bit line or bit line-bar node slowly to minimize the inductive coupling noise and VDD, Ground bouncing, hence allows smaller amount of differential voltage input to the sense amplifier and results in lower power consumption. A self-timer counts the needed time and sends a signal to enable the current driven sense amplifier and to pull down the word line to avoid further pulling up the bit line or bit line-bar voltage and to reduce the power dissipation. A delay device coupling between the self-timer and bit line and bit line-bar avoids overlapping of pull-down and word line and reduces power leakage.

Abstract: An apparatus and method are disclosed for activating a memory location within a memory device. In an apparatus aspect of the invention, a memory device is disclosed. The memory device includes an enable unit arranged to receive a plurality of address signals and a clock signal and to output an activation signal. The address signals has an associated worst case delay, and the enable unit is further arranged to generate an enable signal that is delayed from the clock signal by at least about the worst case delay. The memory device further includes a memory array arranged to receive the activation signal in response to which a corresponding memory location is activated.

Abstract: An electronic memory. The electronic memory includes memory cells and corresponding reference memory cells. Wordlines are connected to the memory cells and the corresponding reference memory cells. If an accessed memory cell has previously been programmed to a first state, an output from the memory cell is connected to a bitline. An output from a selected reference memory cell is connected to a reference bitline. The bitline and the reference bitline are connected to a differential input sense amplifier. The differential input sense amplifier detects the voltage differential between the bitline and the reference bitline. If the memory cell is accessed and the memory cell is in the first state, the memory cell drives the voltage potential on the bitline from a precharge voltage to a discharge voltage at a first rate.