Abstract: A wearable display device, including an optical waveguide element and a projection device, is provided. The projection device includes an optical engine main body, a light emitting unit, an optical combiner, a projection lens, and a connection assembly. The light emitting unit is connected to the optical engine main body and configured to emit an illumination beam. The optical combiner is disposed in the optical engine main body, located on a transmission path of the illumination beam, and configured to guide the illumination beam to form an image beam. The projection lens is connected to the optical engine main body, located on a transmission path of the image beam, and configured to project the image beam. The connection assembly includes a flexible circuit board and a system connector. The light emitting unit is connected to the flexible circuit board and electrically connected to the system connector.

Abstract: An adjustable dumbbell includes a handle assembly and weight assemblies. The weight assemblies connect ends of the handle assembly. Each weight assembly includes an outer shell assembly, a counterweight element, and a locking assembly. The outer shell assembly includes a housing, the housing is connected to the handle assembly. A receiving cavity is defined in the housing. An opening communicated with the receiving cavity is defined at a side of the housing facing the handle assembly. The counterweight element is detachably received in the receiving cavity. The counterweight is fixed with the outer shell assembly by the locking element. The adjustable dumbbell of the disclosure hides the counterweight element, locking element, and two ends of the handle assembly in the outer shell element, prevents the counterweight element from shaking and making abnormal noise due to collision, and raising appearance beauty of the adjustable dumbbell.

Abstract: A fabricating method of reducing photoresist footing includes providing a silicon nitride layer. Later, a fluorination process is performed to graft fluoride ions onto a top surface of the silicon nitride layer. After the fluorination process, a photoresist is formed to contact the top surface of the silicon nitride layer. Finally, the photoresist is patterned to remove at least part of the photoresist contacting the silicon nitride layer.

Abstract: A method includes forming a dummy gate stack over a semiconductor region, forming a source/drain region on a side of the dummy gate stack, removing the dummy gate stack to form a trench, forming a gate dielectric layer extending into the trench and on the semiconductor region, and depositing a fist work-function layer over the gate dielectric layer. The work-function layer comprises a metal selected from the group consisting of ruthenium, molybdenum, and combinations thereof. The method further includes depositing a conductive filling layer over the first work-function layer, and performing a planarization process to remove excess portions of the conductive filling layer, the first work-function layer, and the gate dielectric layer to form a gate stack.

Abstract: A high electron mobility transistor including a substrate; a channel layer on the substrate; an electron supply layer on the channel layer; a dielectric passivation layer on the electron supply layer; a gate recess in the dielectric passivation layer and the electron supply layer; a surface modification layer on an interior surface of the gate recess; and a P-type GaN layer in the gate recess and on the surface modification layer. The surface modification layer has a gradient silicon concentration.

Abstract: A semiconductor package structure includes a package substrate, a semiconductor die, an interposer, an adhesive layer, and a molding material. The semiconductor die is disposed over the package substrate. The interposer is disposed over the semiconductor die. The adhesive layer connects the semiconductor die and the interposer. The molding material surrounds the semiconductor die and the adhesive layer.

Abstract: A method includes forming a dielectric layer over a source/drain region. An opening is formed in the dielectric layer. The opening exposes a portion of the source/drain region. A conductive liner is formed on sidewalls and a bottom of the opening. A surface modification process is performed on an exposed surface of the conductive liner. The surface modification process forms a surface coating layer over the conductive liner. The surface coating layer is removed to expose the conductive liner. The conductive liner is removed from the sidewalls of the opening. The opening is filled with a conductive material in a bottom-up manner. The conductive material is in physical contact with a remaining portion of the conductive liner and the dielectric layer.

Abstract: The present invention relates to compounds with high chemical stability and methods for inhibiting the pathological activity of extracellular histones in a subject. In particular, the invention relates to compounds with high chemical stability, uses thereof and methods for inhibiting or ameliorating extracellular histone mediated ailments (such as, for example, sepsis, systemic immune response syndrome (SIRS) and ischemia reperfusion injury (IRO). More particularly, the invention relates to methods and uses of a polyanionic sulfated cellobioside modified with a small uncharged glycosidically linked substituent at its reducing terminus, wherein the presence of the substituent results in a molecule with high chemical stability without affecting the ability of the molecule to be effective in the therapy of extracellular histone mediated ailments. For example, the present invention relates to methods and uses of ?-O-methyl cellobioside sulfate (mCBS) or a pharmaceutically acceptable salt thereof (e.g.

Abstract: Techniques described herein enable respective (different) types of metal silicide layers to be formed for p-type source/drain regions and n-type source/drain regions in a selective manner. For example, a p-type metal silicide layer may be selectively formed over a p-type source/drain region (e.g., such that the p-type metal silicide layer is not formed over the n-type source/drain region) and an n-type metal silicide layer may be formed over the n-type source/drain region (which may be selective or non-selective). This provides a low Schottky barrier height between the p-type metal silicide layer and the p-type source/drain region, as well as a low Schottky barrier height between the n-type metal silicide layer and the n-type source/drain region. This reduces the contact resistance for both p-type source/drain regions and n-type source/drain regions.

Abstract: A method including: providing a design data of an integrated circuit (IC), the design data comprising a first cell; identifying a first conductive line in the first cell as a critical internal net of the first cell, wherein the first conductive line is electrically connected between an input terminal of the first cell and an output terminal of the first cell; providing a library of the first cell, wherein the library includes a table of timing or power parameters of the first cell based on a multidimensional input set associated with the critical internal net; updating the design data by determining a timing or power value of the first cell based on the table; performing a timing analysis on the updated design data; and forming a photomask based on the updated design data.

Abstract: A method for forming a high electron mobility transistor is disclosed. A substrate is provided. A channel layer is formed on the substrate. An electron supply layer is formed on the channel layer. A dielectric passivation layer is formed on the electron supply layer. A gate recess is formed into the dielectric passivation layer and the electron supply layer. A surface modification layer is conformally deposited on an interior surface of the gate recess. The surface modification layer is first subjected to the nitride treatment and is then subjected to the oxidation treatment. A P-type GaN layer is formed in the gate recess and on the surface modification layer.

Abstract: A wafer bonding device includes: a first fixing apparatus fixing a first wafer, on which a first alignment mark is disposed; a second fixing apparatus fixing a second wafer, on which a second alignment mark is disposed, the second fixing apparatus being disposed opposite to the first fixing apparatus; a reflection member between the first and second fixing apparatuses; a mark reader which reads position information about the first and second alignment marks by means of the reflection member, for aligning the first wafer with the second wafer; and a heating apparatus, configured to heat the first wafer or the second wafer to thermally expand the first wafer or the second wafer so that the first alignment mark or the second alignment mark is located at a central position of a field of view of the mark reader. A wafer bonding method also is involved.

Abstract: A device for wafer bonding alignment includes: a first fixing apparatus, configured to fix a first wafer, a first alignment mark being disposed on the first wafer; a second fixing apparatus, configured to fix a second wafer, a second alignment mark being disposed on the second wafer, the second fixing apparatus being disposed opposite to the first fixing apparatus; a reflection apparatus, located between the first fixing apparatus and the second fixing apparatus; and a mark reader, reading position information of the first alignment mark and the second alignment mark using the reflection apparatus to align the first wafer fixed on the first fixing apparatus and the second wafer fixed on the second fixing apparatus.

Abstract: A method includes forming a dielectric layer over an epitaxial source/drain region. An opening is formed in the dielectric layer. The opening exposes a portion of the epitaxial source/drain region. A barrier layer is formed on a sidewall and a bottom of the opening. An oxidation process is performing on the sidewall and the bottom of the opening. The oxidation process transforms a portion of the barrier layer into an oxidized barrier layer and transforms a portion of the dielectric layer adjacent to the oxidized barrier layer into a liner layer. The oxidized barrier layer is removed. The opening is filled with a conductive material in a bottom-up manner. The conductive material is in physical contact with the liner layer.

Abstract: A Non Conductive Film (NCF) at least includes a first film layer and a second film layer. A surface of the first film layer is provided with a grid-shaped groove structure, and a depth of each groove of the groove structure is less than a thickness of the first film layer. The second film layer is located in the groove in the surface of the first film layer. The fluidity of the first film layer is greater than the fluidity of the second film layer under the same condition.

Abstract: A method for forming a high electron mobility transistor is disclosed. A substrate is provided. A channel layer is formed on the substrate. An electron supply layer is formed on the channel layer. A dielectric passivation layer is formed on the electron supply layer. A gate recess is formed into the dielectric passivation layer and the electron supply layer. A surface modification layer is conformally deposited on an interior surface of the gate recess. The surface modification layer is then subjected to an oxidation treatment or a nitridation treatment. A P-type GaN layer is formed in the gate recess and on the surface modification layer.

Abstract: An HEMT includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer is different from the composition of the second III-V compound layer. A trench is disposed within the first III-V compound layer and the second III-V compound layer. The trench has a first corner and a second corner. The first corner and the second corner are disposed in the first III-V compound layer. A first dielectric layer contacts a sidewall of the first corner. A second dielectric layer contacts a sidewall of the second corner. The first dielectric layer and the second dielectric layer are outside of the trench. A gate is disposed in the trench. A source electrode and a drain electrode are respectively disposed at two sides of the gate. A gate electrode is disposed directly on the gate.

Abstract: A nitrogen plasma treatment is used on an adhesion layer of a contact plug. As a result of the nitrogen plasma treatment, nitrogen is incorporated into the adhesion layer. When a contact plug is deposited in the opening, an interlayer of a metal nitride is formed between the contact plug and the adhesion layer. A nitrogen plasma treatment is used on an opening in an insulating layer. As a result of the nitrogen plasma treatment, nitrogen is incorporated into the insulating layer at the opening. When a contact plug is deposited in the opening, an interlayer of a metal nitride is formed between the contact plug and the insulating layer.

Abstract: A semiconductor structure and a method for manufacturing a semiconductor structure are provided. The method includes: a base is provided, in which the base includes top layer silicon and bottom layer silicon; a device layer is formed on the top layer silicon of the base; a through via penetrating through the device layer and the top layer silicon and extending into the bottom layer silicon is formed; the through via is filled to form a conductive pillar; and preprocessing is performed on the bottom layer silicon of the base to expose the conductive pillar to form a Through Silicon Via (TSV), in which the bottom layer silicon is configured to block a metal contaminant generated in the preprocessing.

Abstract: Techniques described herein enable respective (different) types of metal silicide layers to be formed for p-type source/drain regions and n-type source/drain regions in a selective manner. For example, a p-type metal silicide layer may be selectively formed over a p-type source/drain region (e.g., such that the p-type metal silicide layer is not formed over the n-type source/drain region) and an n-type metal silicide layer may be formed over the n-type source/drain region (which may be selective or non-selective). This provides a low Schottky barrier height between the p-type metal silicide layer and the p-type source/drain region, as well as a low Schottky barrier height between the n-type metal silicide layer and the n-type source/drain region. This reduces the contact resistance for both p-type source/drain regions and n-type source/drain regions.