Patents by Inventor Chih-Wei Lu

Chih-Wei Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • INTEGRATED CHIP WITH CAVITY STRUCTURE
    Publication number: 20220336263
    Abstract: The present disclosure relates to an integrated chip. The integrated chip comprises a dielectric layer over a substrate. A first metal feature is over the dielectric layer. A second metal feature is over the dielectric layer and is laterally adjacent to the first metal feature. A first dielectric liner segment extends laterally between the first metal feature and the second metal feature along an upper surface of the dielectric layer. The first dielectric liner segment extends continuously from along the upper surface of the dielectric layer, to along a sidewall of the first metal feature that faces the second metal feature, and to along a sidewall of the second metal feature that faces the first metal feature. A first cavity is laterally between sidewalls of the first dielectric liner segment and is above an upper surface of the first dielectric liner segment.
    Type: Application
    Filed: June 30, 2022
    Publication date: October 20, 2022
    Inventors: Hsi-Wen Tien, Chung-Ju Lee, Chih Wei Lu, Hsin-Chieh Yao, Shau-Lin Shue, Yu-Teng Dai, Wei-Hao Liao
  • SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME
    Publication number: 20220310810
    Abstract: A semiconductor structure includes a gate structure over a substrate. The structure also includes source/drain epitaxial structures formed on opposite sides of the gate structure. The structure also includes a contact structure formed over the source/drain epitaxial structure. The structure also includes a first via structure formed over the contact structure. The structure also includes a metal line electrically connected to the first via structure. The structure also includes a spacer layer formed over the sidewall and over a portion of a top surface of the metal line. The structure also includes a second via structure formed over the metal line through the spacer layer.
    Type: Application
    Filed: March 25, 2021
    Publication date: September 29, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Hao LIAO, Hsi-Wen TIEN, Chih-Wei LU, Yu-Teng DAI, Hsin-Chieh YAO, Chung-Ju LEE
  • INTEGRATED CIRCUIT
    Publication number: 20220302376
    Abstract: An integrated circuit includes a substrate, a bottom electrode, a dielectric layer, a metal-containing compound layer, a resistance switching element, and a top electrode. The bottom electrode is over the substrate, the bottom electrode having a bottom portion and a top portion over the bottom portion. The bottom portion of the bottom electrode has a sidewall slanted with respect to a sidewall of the top portion of the bottom electrode. The dielectric layer surrounds the bottom portion of the bottom electrode. The metal-containing compound layer surrounds the top portion of the bottom electrode. A top end of the sidewall of the bottom portion of the bottom electrode is higher than a bottom surface of the metal-containing compound layer. The resistance switching element is over the bottom electrode. The top electrode is over the resistance switching element.
    Type: Application
    Filed: June 6, 2022
    Publication date: September 22, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Hao LIAO, Hsi-Wen TIEN, Chih-Wei LU, Pin-Ren DAI, Chung-Ju LEE
  • Method and Structure for Semiconductor Device Having Gate Spacer Protection Layer
    Publication number: 20220301875
    Abstract: A method of forming a semiconductor device includes providing a precursor. The precursor includes a substrate; a gate stack over the substrate; a first dielectric layer over the gate stack; a gate spacer on sidewalls of the gate stack and on sidewalls of the first dielectric layer; and source and drain (S/D) contacts on opposing sides of the gate stack. The method further includes recessing the gate spacer to at least partially expose the sidewalls of the first dielectric layer but not to expose the sidewalls of the gate stack. The method further includes forming a spacer protection layer over the gate spacer, the first dielectric layer, and the S/D contacts.
    Type: Application
    Filed: June 10, 2022
    Publication date: September 22, 2022
    Inventors: Chih Wei Lu, Chung-Ju Lee, Hai-Ching Chen, Chien-Hua Huang, Tien-I Bao
  • SIDEWALL SPACER STRUCTURE ENCLOSING CONDUCTIVE WIRE SIDEWALLS TO INCREASE RELIABILITY
    Publication number: 20220302025
    Abstract: Some embodiments relate to a method for forming a semiconductor structure, the method includes forming a first dielectric layer over a substrate. A first conductive wire is formed over the first dielectric layer. A spacer structure is formed over the first conductive wire. The spacer structure is disposed along sidewalls of the first conductive wire. A second dielectric layer is deposited over and around the first conductive wire. The spacer structure is spaced between the first conductive wire and the second dielectric layer. A removal process is performed on the spacer structure and the second dielectric layer. An upper surface of the spacer structure is disposed above an upper surface of the first conductive wire.
    Type: Application
    Filed: June 7, 2022
    Publication date: September 22, 2022
    Inventors: Yu-Teng Dai, Chung-Ju Lee, Chih Wei Lu, Hsin-Chieh Yao, Hsi-Wen Tien, Wei-Hao Liao
  • THE NOVEL DOUBLE PATTERNING APPROACH BY DIRECT METAL ETCH
    Publication number: 20220285214
    Abstract: In one embodiment, a method of forming metal interconnects uses a direct metal etch approach to form and fill the metal gap. The method may include directly etching a metal layer to form metal patterns. The metal patterns may be spaced apart from one another by recesses. A dielectric spacer may be formed extending along the sidewalls of each of the recesses. The recesses may be filled with a conductive material to form a second set of metal patterns. By directly etching the metal film, the technique allows for reduced line width roughness. The disclosed structure may have the advantages of increased reliability, better RC performance and reduced parasitic capacitance.
    Type: Application
    Filed: March 4, 2021
    Publication date: September 8, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: HSI-WEN TIEN, Wei-Hao Liao, Yu-Teng Dai, Hsin-Chieh Yao, Chih-Wei Lu, Chung-Ju Lee
  • MAGNETIC TUNNEL JUNCTION DEVICES
    Publication number: 20220271217
    Abstract: A device includes a semiconductor substrate, a bottom conductive line, a bottom electrode, a magnetic tunneling junction (MTJ), and a residue. The bottom conductive line is over the semiconductor substrate. The bottom electrode is over the bottom conductive line. The MTJ is over the bottom electrode. The residue of the MTJ is on the sidewall of the bottom electrode and is spaced apart from the bottom conductive line.
    Type: Application
    Filed: May 9, 2022
    Publication date: August 25, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsi-Wen TIEN, Wei-Hao LIAO, Pin-Ren DAI, Chih-Wei LU, Chung-Ju LEE
  • SELF-ALIGNED CAVITY STRUCUTRE
    Publication number: 20220230963
    Abstract: The present disclosure relates to an integrated chip comprising a pair of first metal lines over a substrate. A first interlayer dielectric (ILD) layer is laterally between the pair of first metal lines. The first ILD layer comprises a first dielectric material. A pair of spacers are on opposite sides of the first ILD layer and are laterally separated from the first ILD layer by a pair of cavities. The pair of spacers comprise a second dielectric material. Further, the pair of cavities are defined by opposing sidewalls of the first ILD layer and sidewalls of the pair of spacers that face the first ILD layer.
    Type: Application
    Filed: April 6, 2022
    Publication date: July 21, 2022
    Inventors: Wei-Hao Liao, Chung-Ju Lee, Chih Wei Lu, Hsi-Wen Tien, Yu-Teng Dai
  • Semiconductor structure and method for forming the same
    Patent number: 11393718
    Abstract: A method for forming a semiconductor structure includes forming a first cap layer over a metal layer. The method also includes patterning the metal layer and the first cap layer to form openings exposing the gate structure, and forming a first dielectric layer in the openings, and patterning the first cap layer to form a via cap plug over the metal layer. The method also includes forming a second dielectric layer over the via cap plug and the metal layer, and forming a trench in the second dielectric material to expose the via cap plug. The method also includes removing the via cap plug to enlarge the trench and filling the trench with a conductive material.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: July 19, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hwei-Jay Chu, Chieh-Han Wu, Cheng-Hsiung Tsai, Chih-Wei Lu, Chung-Ju Lee
  • IMAGE REGISTRATION METHOD AND SYSTEM THEREOF
    Publication number: 20220211273
    Abstract: Provided herein are image registration methods comprising providing a wide view image of a target area by a first imager; providing a narrow view image of the target area by a second imager; aligning the narrow view image on the wide view image of the target area; capturing an optical image by an optical imager, wherein the optical imager is configured to locate the optical image in the narrow view image; and displaying the position of the optical image on the narrow view image and the wide view image of the target area; and the systems thereof.
    Type: Application
    Filed: April 30, 2020
    Publication date: July 7, 2022
    Inventors: Chih Wei LU, Sung Wei LU, Jia-Wei LIN, I-Ling CHEN, Tuan Shu HO
  • ATOMIZATION DEVICE
    Publication number: 20220211956
    Abstract: An atomization device includes a liquid storing member that stores a liquid therein, a carrier detachably assembled to the liquid storing member, an opener disposed on at least one of the liquid storing member and the carrier, and an atomizing module that is assembled to at least one of the liquid storing member and the carrier. The opener is configured to form an opening on the liquid storing member. The atomization device has a buffering chamber arranged between the atomizing module and the opening of the liquid storing member, and a volume of the buffering chamber is less than a volume of the liquid. The liquid storing member can be pressed to change an inner pressure thereof, such that a part of the liquid is driven to flow from the opening into the buffering chamber for an atomizing process of the atomizing module.
    Type: Application
    Filed: April 22, 2020
    Publication date: July 7, 2022
    Inventors: SHU-PIN HSIEH, CHIEN-HUA LIN, CHIH-WEI LU, CHI-SHAN HUNG, JO-LING WU
  • OPTICAL SYSTEM AND DETECTION METHOD THEROF
    Publication number: 20220214532
    Abstract: The present invention provides an optical imaging system having an optical module to project the light onto the sample evenly and effectively. In addition, the present invention provides a method to eliminate image artifacts and improve image quality of an invention optical imaging system disclosed herewith.
    Type: Application
    Filed: May 8, 2020
    Publication date: July 7, 2022
    Inventors: Tuan-Shu HO, Chih-Wei LU
  • Sidewall spacer structure enclosing conductive wire sidewalls to increase reliability
    Patent number: 11362030
    Abstract: Some embodiments relate to a semiconductor structure including a first inter-level dielectric (ILD) layer overlying a substrate. A lower conductive via is disposed within the first ILD layer. A plurality of conductive wires overlie the first ILD layer. A second ILD layer is disposed laterally between the conductive wires, where the second ILD layer comprises a first material. A sidewall spacer structure is disposed between the second ILD layer and the plurality of conductive wires. The sidewall spacer structure continuously extends along opposing sidewalls of each conductive wire. A top surface of the sidewall spacer structure is vertically above a top surface of the plurality of conductive wires, and the sidewall spacer structure comprises a second material different from the first material.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: June 14, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Teng Dai, Chung-Ju Lee, Chih Wei Lu, Hsin-Chieh Yao, Hsi-Wen Tien, Wei-Hao Liao
  • Integrated circuit
    Patent number: 11355701
    Abstract: An integrated circuit includes a substrate, a dielectric layer, an etch stop layer, a bottom electrode, a resistance switching element, and a top electrode. The dielectric layer is over the substrate. The etch stop layer is over the dielectric layer, in which the dielectric layer has a first portion directly under the etch stop layer. The bottom electrode penetrates through the etch stop layer and the dielectric layer, in which the dielectric layer has a second portion directly under the bottom electrode, and a top of the first portion of the dielectric layer is lower than a top of the second portion of the dielectric layer. The resistance switching element is over the bottom electrode. The top electrode is over the resistance switching element.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: June 7, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Hao Liao, Hsi-Wen Tien, Chih-Wei Lu, Pin-Ren Dai, Chung-Ju Lee
  • SELF-ALIGNED VIA STRUCTURES AND METHODS
    Publication number: 20220165661
    Abstract: Interconnect structures and methods of forming the same are provided. An interconnect structure according to the present disclosure includes a conductive line feature over a substrate, a conductive etch stop layer over the conductive line feature, a contact via over the conductive etch stop layer, and a barrier layer disposed along a sidewall of the conductive line feature, a sidewall of the conductive etch stop layer, and a sidewall of the contact via.
    Type: Application
    Filed: February 14, 2022
    Publication date: May 26, 2022
    Inventors: Chieh-Han Wu, Cheng-Hsiung Tsai, Chih Wei Lu, Chung-Ju Lee
  • Magnetic tunnel junction devices
    Patent number: 11329216
    Abstract: A semiconductor device includes a semiconductor substrate, a bottom electrode, a magnetic tunneling junction (MTJ), a top electrode, and a residue. The bottom electrode is disposed over the semiconductor substrate. The MTJ is disposed over the bottom electrode. The top electrode is disposed over the MTJ layer. Sidewalls of the bottom electrode, the MTJ, and the top electrode are vertically aligned with each other. The residue of the MTJ is located on the sidewall of the bottom electrode.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: May 10, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsi-Wen Tien, Wei-Hao Liao, Pin-Ren Dai, Chih-Wei Lu, Chung-Ju Lee
  • Self-aligned cavity strucutre
    Patent number: 11302641
    Abstract: The present disclosure relates to an integrated chip comprising a pair of first metal lines over a substrate. A first interlayer dielectric (ILD) layer is laterally between the pair of first metal lines. The first ILD layer comprises a first dielectric material. A pair of spacers are on opposite sides of the first ILD layer and are laterally separated from the first ILD layer by a pair of cavities. The pair of spacers comprise a second dielectric material. Further, the pair of cavities are defined by opposing sidewalls of the first ILD layer and sidewalls of the pair of spacers that face the first ILD layer.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: April 12, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Hao Liao, Chung-Ju Lee, Chih Wei Lu, Hsi-Wen Tien, Yu-Teng Dai
  • SEMICONDUCTOR ARRANGEMENT AND METHOD OF MAKING
    Publication number: 20220084875
    Abstract: A semiconductor arrangement is provided. The semiconductor arrangement includes a first dielectric layer over a substrate, a metal layer over the first dielectric layer, a first conductive structure passing through the metal layer and the first dielectric layer, a second conductive structure passing through the metal layer and the first dielectric layer, and a third conductive structure coupling the first conductive structure to the second conductive structure, and overlying a first portion of the metal layer between the first conductive structure and the second conductive structure, wherein an interface exists between the metal layer and at least one of the first conductive structure or the second conductive structure.
    Type: Application
    Filed: November 29, 2021
    Publication date: March 17, 2022
    Inventors: Hsi-Wen TIEN, Wei-Hao LIAO, Pin-Ren DAI, Chih Wei LU, Chung-Ju LEE
  • Optical interference imaging device and its application
    Patent number: 11262183
    Abstract: Provided herein are devices and systems comprising an illumination module configured to provide a source light to an optical interference module, which converts the source light to a line of light and processes light signal; an interference objective module, which handles light from the optical interference module and processes light signal generated from a sample; a two-dimensional camera configured to receive a backscattered interference signal from the sample, and a data processing module which processes the interference signal into an image.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: March 1, 2022
    Assignee: Apollo Medical Optics, Ltd.
    Inventors: Tuan-Shu Ho, I-Ling Chen, Dan Ji, Sung Wei Lu, Tzu Wei Liu, Jen Yu Tseng, Ting Yueh Lin, Chih Wei Lu, Jia-Wei Lin, Yo Cheng Chuang, Sheng-Lung Huang
  • Self-aligned via structures with barrier layers
    Patent number: 11251118
    Abstract: Interconnect structures and methods of forming the same are provided. An interconnect structure according to the present disclosure includes a conductive line feature over a substrate, a conductive etch stop layer over the conductive line feature, a contact via over the conductive etch stop layer, and a barrier layer disposed along a sidewall of the conductive line feature, a sidewall of the conductive etch stop layer, and a sidewall of the contact via.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: February 15, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chieh-Han Wu, Cheng-Hsiung Tsai, Chih Wei Lu, Chung-Ju Lee