Abstract: A semiconductor device includes a substrate having a first conductivity type, a first well formed in the substrate and having a second conductivity type, a first diffusion region formed in the first well and having the first conductivity type, a first interlayer dielectric layer disposed over the first well and the first diffusion region, and a resistor wire formed of a conductive material and embedded in the first interlayer dielectric layer. The resistor wire overlaps the first diffusion region and at least partially overlaps the first well in plan view.

Abstract: The present disclosure provides a method that includes receiving a semiconductor substrate that includes an integrated circuit (IC) cell and a well tape cell surrounding the IC cell; forming first fin active regions in the well tape cell and second fin active regions in the IC cell; forming a hard mask within the well tape cell, wherein the hard mask includes openings that define first source/drain (S/D) regions on the first fin active region of the well tape cell; forming gate stacks on the second fin active regions within the IC cell and absent from the well tape cell, wherein the gate stacks define second S/D regions on the second fin active regions; epitaxially growing first S/D features in the first S/D regions using the hard mask to constrain the epitaxially growing; and forming contacts landing on the first S/D features within the well tape cell.

Abstract: A semiconductor structure includes a fin active region extruded from a semiconductor substrate; and a gate stack disposed on the fin active region. The gate stack includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. The gate dielectric layer includes a first dielectric material. The semiconductor structure further includes a dielectric gate of a second dielectric material disposed on the fin active region. The gate dielectric layer extends from a sidewall of the gate electrode to a sidewall of the dielectric gate. The second dielectric material is different from the first dielectric material in composition.

Abstract: A semiconductor structure includes a fin active region extruded from a semiconductor substrate; and a gate stack disposed on the fin active region. The gate stack includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. The gate dielectric layer includes a first dielectric material. The semiconductor structure further includes a dielectric gate of a second dielectric material disposed on the fin active region. The gate dielectric layer extends from a sidewall of the gate electrode to a sidewall of the dielectric gate. The second dielectric material is different from the first dielectric material in composition.

Abstract: A structure and a formation method of a semiconductor device are provided. The method includes forming a first semiconductor fin and a second semiconductor fin over a semiconductor substrate. The second semiconductor fin is wider than the first semiconductor fin. The method also includes forming a gate stack over the semiconductor substrate, and the gate stack extends across the first semiconductor fin and the second semiconductor fin. The method further includes forming a first source/drain structure on the first semiconductor fin, and the first source/drain structure is p-type doped. In addition, the method includes forming a second source/drain structure on the second semiconductor fin, and the second source/drain structure is n-type doped.

Abstract: The first type of semiconductor device includes a first fin structure extending in a first direction, a first gate, and a first slot contact disposed over the first fin structure. The first gate extends in a second direction and has a first gate dimension measured in the first direction. The first slot contact has a first slot contact dimension measured in the first direction. A second type of semiconductor device includes: a second fin structure extending in a third direction, a second gate, and a second slot contact disposed over the second fin structure. The second gate extends in a fourth direction and has a second gate dimension measured in the third direction. The second slot contact has a second slot contact dimension measured in the third direction. The second slot contact dimension is greater than the second gate dimension and greater than the first slot contact dimension.

Abstract: Examples of an integrated circuit with a capacitor structure and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate and a trench isolation material disposed on the substrate. An isolation structure is disposed on the trench isolation material. A first electrode disposed on the isolation structure, and a second electrode disposed on the isolation structure. A capacitor dielectric is disposed on the isolation structure between the first electrode and the second electrode. In some such examples, the isolation structure includes a first hard mask disposed on the trench isolation material, a dielectric disposed on the first hard mask, and a second hard mask disposed on the dielectric.

Abstract: Semiconductor structures are provided. A semiconductor structure includes a substrate, a conductive plate of a first metal layer over the substrate, a first resistor material of a resistor layer over the conductive plate, a high-K material formed between the first resistor material and the conductive plate, a first conductive line of a second metal layer over the resistor layer, and a first via formed between the first conductive line and the first resistor material. The conductive plate, the first resistor material and the high-K material form a capacitor between the first and second metal layers. The first distance between the first resistor material and the conductive plate is less than the second distance between the first resistor material and the first conductive line.

Abstract: A first and a second gate structure each extend in a first direction. A first and a second conductive contact extend in the first direction and are separated from the first and second gate structures in a second direction. A first isolation structure extends in the second direction and separates the first gate structure from the second gate structure. A second isolation structure extends in the second direction and separates the first conductive contact from the second conductive contact. The first gate structure is electrically coupled to a first electrical node. The second gate structure is electrically coupled to a second electrical node different from the first electrical node. The first conductive contact is electrically coupled to the second electrical node. The second conductive contact is electrically coupled to the first electrical node.

Abstract: The present disclosure provides a method that includes receiving a semiconductor substrate that includes an integrated circuit (IC) cell and a well tape cell surrounding the IC cell; forming first fin active regions in the well tape cell and second fin active regions in the IC cell; forming a hard mask within the well tape cell, wherein the hard mask includes openings that define first source/drain (S/D) regions on the first fin active region of the well tape cell; forming gate stacks on the second fin active regions within the IC cell and absent from the well tape cell, wherein the gate stacks define second S/D regions on the second fin active regions; epitaxially growing first S/D features in the first S/D regions using the hard mask to constrain the epitaxially growing; and forming contacts landing on the first S/D features within the well tape cell.

Abstract: A semiconductor device includes a substrate having a first conductivity type, a first well formed in the substrate and having a second conductivity type, a first diffusion region formed in the first well and having the first conductivity type, a first interlayer dielectric layer disposed over the first well and the first diffusion region, and a resistor wire formed of a conductive material and embedded in the first interlayer dielectric layer. The resistor wire overlaps the first diffusion region and at least partially overlaps the first well in plan view.

Abstract: A semiconductor structure includes a fin active region extruded from a semiconductor substrate; and a gate stack disposed on the fin active region. The gate stack includes a gate dielectric layer and a gate electrode disposed on the gate dielectric layer. The gate dielectric layer includes a first dielectric material. The semiconductor structure further includes a dielectric gate of a second dielectric material disposed on the fin active region. The gate dielectric layer extends from a sidewall of the gate electrode to a sidewall of the dielectric gate. The second dielectric material is different from the first dielectric material in composition.

Abstract: A semiconductor device includes a substrate having a first conductivity type, a first well formed in the substrate and having a second conductivity type, a first diffusion region formed in the first well and having the first conductivity type, a first interlayer dielectric layer disposed over the first well and the first diffusion region, and a resistor wire formed of a conductive material and embedded in the first interlayer dielectric layer. The resistor wire overlaps the first diffusion region and at least partially overlaps the first well in plan view.

Abstract: A semiconductor device having a hybrid doping distribution and a method of fabricating the semiconductor device are presented. The semiconductor device includes a gate disposed over an active semiconducting region and a first S/D region and a second S/D region each aligned to opposing sides of the gate side walls. The active semiconducting region has a doping profile that includes a first doping region at a first depth beneath the gate and having a first dopant concentration. The doping profile includes a second doping region at a second depth beneath the gate greater than the first depth and having a second dopant concentration less than the first dopant concentration.

Abstract: A semiconductor device includes a substrate having a first conductivity type, a first well formed in the substrate and having a second conductivity type, a first diffusion region formed in the first well and having the first conductivity type, a first interlayer dielectric layer disposed over the first well and the first diffusion region, and a resistor wire formed of a conductive material and embedded in the first interlayer dielectric layer. The resistor wire overlaps the first diffusion region and at least partially overlaps the first well in plan view.

Abstract: A semiconductor device having a hybrid doping distribution and a method of fabricating the semiconductor device are presented. The semiconductor device includes a gate disposed over an active semiconducting region and a first S/D region and a second S/D region each aligned to opposing sides of the gate side walls. The active semiconducting region has a doping profile that includes a first doping region at a first depth beneath the gate and having a first dopant concentration. The doping profile includes a second doping region at a second depth beneath the gate greater than the first depth and having a second dopant concentration less than the first dopant concentration.

Abstract: A semiconductor device includes a substrate having a first conductivity type, a first well formed in the substrate and having a second conductivity type, a first diffusion region formed in the first well and having the first conductivity type, a first interlayer dielectric layer disposed over the first well and the first diffusion region, and a resistor wire formed of a conductive material and embedded in the first interlayer dielectric layer. The resistor wire overlaps the first diffusion region and at least partially overlaps the first well in plan view.

Abstract: A semiconductor device having a hybrid doping distribution and a method of fabricating the semiconductor device are presented. The semiconductor device includes a gate disposed over an active semiconducting region and a first S/D region and a second S/D region each aligned to opposing sides of the gate side walls. The active semiconducting region has a doping profile that includes a first doping region at a first depth beneath the gate and having a first dopant concentration. The doping profile includes a second doping region at a second depth beneath the gate greater than the first depth and having a second dopant concentration less than the first dopant concentration.

Abstract: Disclosed herein is an aqueous tissue clearing solution for making a biological material, such as a tissue or an organ of an animal, or a bio-engineered collagen scaffold transparent.

Abstract: A fabrication method for a light-emitting element package, the method comprising: providing a high precision wafer level mold module, the high precision wafer level mold module comprising an upper mold and a bottom mold; mounting a substrate with a plurality of light-emitting elements between the upper mold and the bottom mold; filling package materials into the high precision wafer level mold module to obtain package members mounted on the light-emitting elements; and removing the high precision wafer level mold module.