Patents by Inventor Chi-Hung Lin

Chi-Hung Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240173819
    Abstract: A wafer grinding parameter optimization method and an electronic device are provided. The method includes the following. A natural frequency of a grinding wheel spindle of wafer processing equipment is obtained, and a grinding stability lobe diagram is generated accordingly. A grinding speed is selected based on a speed range of the grinding wheel spindle. Multiple grinding parameter combinations are determined based on the grinding speed. Multiple grinding simulation result combinations corresponding to the grinding parameter combinations are generated. A specific grinding parameter combination is selected based on each of the grinding simulation result combinations, and the wafer processing equipment is set accordingly.
    Type: Application
    Filed: September 12, 2023
    Publication date: May 30, 2024
    Applicant: GlobalWafers Co., Ltd.
    Inventors: Chih-Chun Cheng, Wen-Nan Cheng, Meng-Bi Lin, Chi-Feng Li, Tzu-Fan Chiang, Wei-Jen Chen, Chien Hung Chen, Hsiu Chi Liang, Ying-Ru Shih
  • Publication number: 20240178091
    Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.
    Type: Application
    Filed: February 7, 2024
    Publication date: May 30, 2024
    Inventors: Tzu-Sung Huang, Ming Hung Tseng, Yen-Liang Lin, Hao-Yi Tsai, Chi-Ming Tsai, Chung-Shi Liu, Chih-Wei Lin, Ming-Che Ho
  • Patent number: 11988972
    Abstract: A method is described. The method includes obtaining a relationship between a thickness of a contamination layer formed on a mask and an amount of compensation energy to remove the contamination layer, obtaining a first thickness of a first contamination layer formed on the mask from a thickness measuring device, and applying first compensation energy calculated from the relationship to a light directed to the mask.
    Type: Grant
    Filed: February 13, 2023
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Hsun Lin, Yu-Hsiang Ho, Jhun Hua Chen, Chi-Hung Liao, Teng Kuei Chuang
  • Patent number: 11990836
    Abstract: A power supply system with dynamic current sharing includes a current-sharing bus and a plurality of power supply units connected to each other through the current-sharing bus. The current-sharing bus provides a first current signal. Each power supply unit includes a local current bus for providing a second current signal. The active current-sharing unit compares the first current signal with the second current signal to generate a compensation voltage. The current-averaging unit compares a difference value between an average value of the first current signal and an average value of the second current signal to generate an average voltage. The droop current unit receives the second current signal to generate a droop compensation voltage. The integration calculation unit makes output currents of the power supply units be approximately equal according to the compensation voltage, the average voltage, and the droop compensation voltage.
    Type: Grant
    Filed: April 5, 2022
    Date of Patent: May 21, 2024
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Chi-Hung Lin, Guo-Hua Wang, Yu-Jie Lin, Hsien-Kai Wang
  • Publication number: 20240163947
    Abstract: A method for multi-link operation (MLO) is provided. The method for MLO may be applied to an apparatus. The method for MLO may include the following steps. A multi-chip controller of the apparatus may assign different data to a plurality of chips of the apparatus, wherein each chip corresponds to one link of multi-links. Each chip may determine whether transmission of the assigned data has failed. A first chip of the chips may transmit the assigned data to an access point (AP) in response to the first chip determining that the transmission of the assigned data has not failed.
    Type: Application
    Filed: November 8, 2023
    Publication date: May 16, 2024
    Inventors: Cheng-Ying WU, Wei-Wen LIN, Shu-Min CHENG, Hui-Ping TSENG, Chi-Han HUANG, Chih-Chun KUO, Yang-Hung PENG, Hao-Hua KANG
  • Patent number: 11983475
    Abstract: A semiconductor device includes: M*1st conductors in a first layer of metallization (M*1st layer) and being aligned correspondingly along different corresponding ones of alpha tracks and representing corresponding inputs of a cell region in the semiconductor device; and M*2nd conductors in a second layer of metallization (M*2nd layer) aligned correspondingly along beta tracks, and the M*2nd conductors including at least one power grid (PG) segment and one or more of an output pin or a routing segment; and each of first and second ones of the input pins having a length sufficient to accommodate at most two access points; each of the access points of the first and second input pins being aligned to a corresponding different one of first to fourth beta tracks; and the PG segment being aligned with one of the first to fourth beta tracks.
    Type: Grant
    Filed: February 7, 2023
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Pin-Dai Sue, Po-Hsiang Huang, Fong-Yuan Chang, Chi-Yu Lu, Sheng-Hsiung Chen, Chin-Chou Liu, Lee-Chung Lu, Yen-Hung Lin, Li-Chun Tien, Yi-Kan Cheng
  • Publication number: 20240147376
    Abstract: Apparatus and methods are provided for thermal throttling for UE configured with multi-panel transceiving on FR2. In one novel aspect, the UE prioritizes throttling actions based on signal qualities of each transceiving panel. In one embodiment, the switching to the target panel from the active panel is selected as the highest priority throttling action when the signal quality of the target panel is similar to the active panel. In another embodiment, the UE further determines if the quality of the target panel is sufficient to support mmW transceiving before switching to the target panel. In one embodiment, the UE reduces one or more antennae of an active panel when the signal quality difference between the active panel and the target panel is bigger than a predefined gap threshold.
    Type: Application
    Filed: September 22, 2023
    Publication date: May 2, 2024
    Inventors: Chih-Chieh Lai, Feng-Wen Weng, Yu-Hung Huang, Chi-Hsiang Lin
  • Patent number: 11973164
    Abstract: A light-emitting device includes a substrate including a top surface; a semiconductor stack including a first semiconductor layer, an active layer and a second semiconductor layer formed on the substrate, wherein a portion of the top surface is exposed; a distributed Bragg reflector (DBR) formed on the semiconductor stack and contacting the portion of the top surface of the substrate; a metal layer formed on the distributed Bragg reflector (DBR), contacting the portion of the top surface of the substrate and being insulated with the semiconductor stack; and an insulation layer formed on the metal layer and contacting the portion of the top surface of the substrate.
    Type: Grant
    Filed: January 3, 2023
    Date of Patent: April 30, 2024
    Assignee: EPISTAR CORPORATION
    Inventors: Che-Hung Lin, Chien-Chih Liao, Chi-Shiang Hsu, De-Shan Kuo, Chao-Hsing Chen
  • Publication number: 20240128127
    Abstract: A semiconductor device includes a single diffusion break (SDB) structure dividing a fin-shaped structure into a first portion and a second portion, an isolation structure on the SDB structure, a first spacer adjacent to the isolation structure, a metal gate adjacent to the isolation structure, a shallow trench isolation (STI around the fin-shaped structure, and a second isolation structure on the STI. Preferably, a top surface of the first spacer is lower than a top surface of the isolation structure and a bottom surface of the first spacer is lower than a bottom surface of the metal gate.
    Type: Application
    Filed: December 28, 2023
    Publication date: April 18, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Ssu-l Fu, Chun-ya Chiu, Chi-Ting Wu, Chin-HUNG Chen, Yu-Hsiang Lin
  • Patent number: 11957722
    Abstract: The present invention discloses an anti-aging composition, which includes: (a) isolated lactic acid bacterial strains or a fermented product thereof; and (b) an excipient, a diluent, or a carrier; wherein the isolated lactic acid bacterial strains include: Bifidobacterium bifidum VDD088 strains, Bifidobacterium breve Bv-889 strains, and Bifidobacterium longum BLI-02 strains. The present invention further provides a method for preventing aging by administering the foregoing anti-aging composition to a subject in need thereof.
    Type: Grant
    Filed: March 7, 2022
    Date of Patent: April 16, 2024
    Assignee: GLAC BIOTECH CO., LTD
    Inventors: Hsieh-Hsun Ho, Yi-Wei Kuo, Wen-Yang Lin, Jia-Hung Lin, Yen-Yu Huang, Chi-Huei Lin, Shin-Yu Tsai
  • Patent number: 11935804
    Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.
    Type: Grant
    Filed: April 10, 2023
    Date of Patent: March 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tzu-Sung Huang, Ming Hung Tseng, Yen-Liang Lin, Hao-Yi Tsai, Chi-Ming Tsai, Chung-Shi Liu, Chih-Wei Lin, Ming-Che Ho
  • Publication number: 20240077914
    Abstract: A foldable electronic device includes a first body having an end and a first inclined surface, a second body having a second inclined surface, and a hinge module. The end includes an accommodating area. A virtual shaft line exists between sides of the first inclined surface and the second inclined surface that are closest to each other. The second body rotates relative to the first body through the virtual shaft line. The hinge module includes a first bracket adjacent to the first inclined surface, connected to the first body, and located in the accommodating area, a second bracket adjacent to the second inclined surface and connected to the second body, and a third bracket including a first end and a second end. The first bracket is connected to the first end through a first torsion assembly. The second bracket is connected to the second end through a second torsion assembly.
    Type: Application
    Filed: April 27, 2023
    Publication date: March 7, 2024
    Applicant: ASUSTeK COMPUTER INC.
    Inventors: Chih-Han Chang, Tsung-Ju Chiang, Chi-Hung Lin, Yen-Ting Liu
  • Patent number: 11872069
    Abstract: A method includes a step of obtaining plural pieces of training data each of which includes a different radiographic image of a bone and each of which has a label indicating one of an overt fracture, an occult fracture and no fracture, a step of using the plural pieces of training data to pre-train a deep convolutional network (DCN) model to obtain a preliminary DCN model, a step of determining a subset of the plural pieces of training data by at least excluding any piece of training data that has a label indicating occult fracture, and a step of using the subset to train the preliminary DCN model to obtain a first DCN model.
    Type: Grant
    Filed: March 8, 2021
    Date of Patent: January 16, 2024
    Assignee: Chang Gung Memorial Hospital, Linkou
    Inventors: Chi-Hung Lin, Kevin C. Chung, Chang-Fu Kuo
  • Patent number: 11658670
    Abstract: The systems and methods discussed herein related to digital to analog conversion. A digital to analog conversion circuit can includes a digital input, an analog output, and a cell array. The digital to analog converter can also include an integrator, an analog to digital converter (ADC), and a summer coupled to the ADC, and an adaptation circuit coupled to the summer. The adaption circuit provides controls signals to the cell array.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: May 23, 2023
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Koon Lun Jackie Wong, Chi-Hung Lin
  • Publication number: 20230147990
    Abstract: A power supply system with dynamic current sharing includes a current-sharing bus and a plurality of power supply units connected to each other through the current-sharing bus. The current-sharing bus provides a first current signal. Each power supply unit includes a local current bus for providing a second current signal. The active current-sharing unit compares the first current signal with the second current signal to generate a compensation voltage. The current-averaging unit compares a difference value between an average value of the first current signal and an average value of the second current signal to generate an average voltage. The droop current unit receives the second current signal to generate a droop compensation voltage. The integration calculation unit makes output currents of the power supply units be approximately equal according to the compensation voltage, the average voltage, and the droop compensation voltage.
    Type: Application
    Filed: April 5, 2022
    Publication date: May 11, 2023
    Inventors: Chi-Hung LIN, Guo-Hua WANG, Yu-Jie LIN, Hsien-Kai WANG
  • Patent number: 11527504
    Abstract: External electrical connectors and methods of forming such external electrical connectors are discussed. A method includes forming an external electrical connector structure on a substrate. The forming the external electrical connector structure includes plating a pillar on the substrate at a first agitation level affected at the substrate in a first solution. The method further includes plating solder on the external electrical connector structure at a second agitation level affected at the substrate in a second solution. The second agitation level affected at the substrate is greater than the first agitation level affected at the substrate. The plating the solder further forms a shell on a sidewall of the external electrical connector structure.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: December 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Fu Shih, Chun-Yen Lo, Cheng-Lin Huang, Wen-Ming Chen, Chien-Ming Huang, Yuan-Fu Liu, Yung-Chiuan Cheng, Wei-Chih Huang, Chen-Hsun Liu, Chien-Pin Chan, Yu-Nu Hsu, Chi-Hung Lin, Te-Hsun Pang, Chin-Yu Ku
  • Patent number: 11494698
    Abstract: A method and an electronic device for selecting influence indicators by using an automatic mechanism are provided. The method includes following steps. Raw data is obtained, where the raw data includes a body-related variable and a plurality of to-be-measured indicators corresponding to the body-related variable. The body-related variable is set as a target parameter. The body-related variable and the to-be-measured indicators are input into a plurality of validation models, and the to-be-measured indicators are sorted according an output result of the validation models to obtain ranking data. Importance of the to-be-measured indicators is calculated by using a screening condition according to the ranking data, so as to select a candidate indicator from the to-be-measured indicators. An influence indicator is determined by calculating a correlation between the candidate indicator and the body-related variable.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: November 8, 2022
    Assignees: Acer Incorporated, National Yang-Ming University
    Inventors: Zong-Han Tsai, Tsung-Hsien Tsai, Liang-Kung Chen, Li-Ning Peng, Ting-Fen Tsai, Chi-Hung Lin, Chien-Yi Tung, Wei-Ju Lin
  • Publication number: 20220239303
    Abstract: The systems and methods discussed herein related to digital to analog conversion. A digital to analog conversion circuit can includes a digital input, an analog output, and a cell array. The digital to analog converter can also include an integrator, an analog to digital converter (ADC), and a summer coupled to the ADC, and an adaptation circuit coupled to the summer. The adaption circuit provides controls signals to the cell array.
    Type: Application
    Filed: January 28, 2021
    Publication date: July 28, 2022
    Applicant: Avago Technologies International Sales Pte. Limited
    Inventors: Koon Lun Jackie Wong, Chi-Hung Lin
  • Patent number: 11223286
    Abstract: A method for estimating an output voltage of an isolated resonant converter is disclosed. The proposed method, wherein the isolated resonant converter includes a transformer having an auxiliary winding and a secondary winding, a first output diode electrically connected to the secondary winding in series and a voltage holder coupled to the auxiliary winding, includes: obtaining the output voltage V o = [ v aux_dh ? ( t ) + V F ] ยท N s N aux - V F , where vaux_dh(t) is an output voltage of the voltage holder, VF is a forward voltage drop of the first output diode, NS is a number of turns of the secondary winding and Naux is a number of turns of the auxiliary winding.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: January 11, 2022
    Assignee: NATIONAL CHENG KUNG UNIVERSITY
    Inventors: Tsorng-Juu Liang, Chi-Hung Lin, Wei-Jing Tseng
  • Patent number: 11145257
    Abstract: A display device driving method, suitable for a driver circuit, includes the following steps: determining magnitude of a plurality of data voltages according to received display data, and the plurality of data voltages are configured to be transmitted to a plurality of pixel circuits via a plurality of data lines; comparing the magnitude of the plurality of data voltages to generate a comparison result; and before providing corresponding ones of the plurality of data voltages to a first pixel group arranged at an i-th row of the plurality of pixel circuits, providing a first reset voltage having a value determined according to the comparison result to the plurality of data lines, or providing a second reset voltage to m data lines selected according to the comparison result from the plurality of data lines, i is a positive integer, and m is an integer.
    Type: Grant
    Filed: February 2, 2020
    Date of Patent: October 12, 2021
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Chieh-Hsiang Chang, Shih-Hsiang Pan, Chi-Hung Lin, Wen-Pin Tsai, Huang-Chin Tang