Abstract: A FIT evaluation method for an IC is provided. The FIT evaluation method includes accessing data representing a layout of the IC comprising a number of metal lines and a number of VIAs; picking a number of nodes along the metal lines; dividing each of the metal lines into a number of metal segments based on the nodes; and determining a FIT value for each of the metal segments or VIAs to verify the layout and fabricate the IC.

Abstract: A semiconductor device includes: a power grid (PG) arrangement including: a conductive layer M(i) including segments which are conductive, where i is an integer and i?0; and a conductive layer M(i+1) over the conductive layer M(i), the conductive layer M(i+1) including segments which are conductive; the M(i) segments including first and second segments designated correspondingly for first and second reference voltages, the first and second segments being interspersed and substantially parallel to a first direction; and the segments in the conductive layer M(i+1) including third and fourth segments designated correspondingly for the first and second reference voltages; the third and fourth segments being interspersed and substantially parallel to a perpendicular second direction; and wherein the segments in the conductive layer M(i+1) are arranged substantially asymmetrically such that each fourth segment is located, relative to the first direction, substantially asymmetrically between corresponding adjacent o

Abstract: Methods for analyzing electromigration (EM) in an integrated circuit (IC) are provided. The layout of the IC is obtained. A metal segment is selected from the layout according to the current simulation result of the IC. It is determined whether to relax the EM rule on the metal segment according to the number of vias over the metal segment in the layout. The vias are in contact with the metal segment.

Abstract: A method of designing an integrated circuit device includes receiving an initial design of an integrated circuit, including a selection and location of a functional group of integrated circuit components, a power grid with multiple layers of conductive lines for supplying power to the components, and vias of one or more initial sizes interconnecting the conductive lines of different layers. The method further includes determining, based on a predetermined criterion such as the existence of unoccupied space for a functional unit, that a via modification can be made. The method further includes substituting the one or more of the via with a modified via of a larger cross-sectional area or a plurality of vias having a larger total cross-sectional area than the initial via. The method further includes confirming that the modified design complies with a predetermined set of design rules.

Abstract: The present disclosure relates to a method of performing electromigration sign-off. The method includes determining a change in temperature due to joule heating from an RMS current of a first interconnect. The change in temperature due to joule heating is added to a change in temperature due to device self-heating to determine a first change in real temperature. A first average current limit is determined for the first interconnect using the first change in real temperature. A first average current on the first interconnect is compared to the first average current limit to determine if a first electromigration violation is present on the first interconnect. A second average current is determined for a second interconnect using a second change in real temperature. The second average current is compared to a second average current limit to determine if a second electromigration violation is present on the second interconnect.

Abstract: A system for simulating reliability of a circuit design includes: a first memory device, arranged to store a technology file, wherein the circuit design comprises a plurality of circuit cells, and the first memory device further stores a plurality of first failure rates corresponding to a first circuit cell in the plurality of circuit cells; a first simulating device, coupled to the first memory device, for generating a first specific failure rate of the first circuit cell according to the plurality of first failure rates and the technology file; and an operating device, coupled to the first simulating device, for generating a total failure rate of the circuit design according to the first specific failure rate.

Abstract: The present disclosure, in some embodiments, relates to an electromigration sign-off tool. The tool includes electronic memory configured to store an integrated chip design and an environmental temperature having a same value corresponding to a plurality of interconnect wires within the integrated chip design. An adder is configured to add the environmental temperature to a plurality of real temperatures to determine a plurality of actual temperatures having different values corresponding to different ones of the plurality of interconnect wires. The plurality of real temperatures account for Joule heating on the plurality of interconnect wires. An average current limit calculation element is configured to determine an average current limit at a first one of the plurality of actual temperatures. A comparator is configured to determine an electromigration violation on a first interconnect wire by comparing the average current limit to an average current of the first interconnect wire.

Abstract: A method includes determining a cell loading of a cell in an integrated circuit (IC) layout diagram. Based on the determined cell loading, a power parameter associated with the cell is determined. In response to the determined power parameter exceeding a design criterion, at least one of altering a placement of the cell in the IC layout diagram or modifying a power delivery path to the cell is performed. At least one of the determining the cell loading, the determining the power parameter, the altering the placement of the cell, or the modifying the power delivery path is executed by a processor.

Abstract: In a method, based on an operating condition of a region of an integrated circuit (IC), a first relationship between a temperature and heating power of the region is determined. Based on a cooling capacity of the region, a second relationship between the temperature and cooling power of the region is determined. Based on the first relationship and the second relationship, it is determined whether the region is thermally stable. In response to a determination that the region is thermally unstable, at least one of a structure or the operating condition of the region is changed. At least one of the determination of the first relationship, the determination of the second relationship, the determination of thermally stability of the region, or the change of at least one of the structure or the operating condition of the region is executed by a processor.

Abstract: A method of designing an integrated circuit device includes receiving an initial design of an integrated circuit, including a selection and location of a functional group of integrated circuit components, a power grid with multiple layers of conductive lines for supplying power to the components, and vias of one or more initial sizes interconnecting the conductive lines of different layers. The method further includes determining, based on a predetermined criterion such as the existence of unoccupied space for a functional unit, that a via modification can be made. The method further includes substituting the one or more of the via with a modified via of a larger cross-sectional area or a plurality of vias having a larger total cross-sectional area than the initial via. The method further includes confirming that the modified design complies with a predetermined set of design rules.

Abstract: A method of determining electromigration (EM) compliance of a circuit is performed. The method includes providing a layout of the circuit, the layout comprising one or more metal lines, and changing a property of one or more of the one or more metal lines within one or more nets of a plurality of nets in the layout. Each of the nets includes a subset of the one or more metal lines. The method also includes determining one or more current values drawn only within the one or more nets and comparing the determined one or more current values drawn with corresponding threshold values. Based on the comparison, an indication is provided whether or not the layout is compliant. A pattern of the one or more metal lines in the compliant layout is transferred to a mask to be used in the manufacturing of the circuit on a substrate.

Abstract: An integrated circuit includes a first set of devices, a set of metal layers and a header circuit. The first set of devices are configured to operate on a first supply voltage, and are located on a first layer of the integrated circuit. The set of metal layers are above the first layer, and includes a first metal layer and a second metal layer. The first metal layer extends in at least a first direction and a second direction. The header circuit is above the first set of devices. At least a portion of the header circuit is positioned between the first metal layer and the second metal layer. The header circuit is configured to provide the first supply voltage to the first set of devices, and is configured to be coupled to a second voltage supply having a second supply voltage different from the first supply voltage.

Abstract: A method performed by at least one processor includes: accessing a layout of an integrated circuit (IC), the layout comprising a resistor-capacitor (RC) netlist comprising a plurality of circuit nodes; identifying an RC network in the RC netlist; determining a characterization matrix corresponding to the RC network; updating the RC netlist by replacing the RC network with the characterization matrix; and calculating voltages and currents of the plurality of circuit nodes based on the updated RC netlist.

Abstract: A method of determining electromigration (EM) compliance of a circuit is performed. The method includes providing a layout of the circuit, the layout comprising one or more metal lines, and changing a property of one or more of the one or more metal lines within one or more nets of a plurality of nets in the layout. Each of the nets includes a subset of the one or more metal lines. The method also includes determining one or more current values drawn only within the one or more nets and comparing the determined one or more current values drawn with corresponding threshold values. Based on the comparison, an indication is provided whether or not the layout is compliant. A pattern of the one or more metal lines in the compliant layout is transferred to a mask to be used in the manufacturing of the circuit on a substrate.

Abstract: The present disclosure, in some embodiments, relates to an electromigration sign-off tool. The tool includes electronic memory configured to store an integrated chip design and an environmental temperature having a same value corresponding to a plurality of interconnect wires within the integrated chip design. An adder is configured to add the environmental temperature to a plurality of real temperatures to determine a plurality of actual temperatures having different values corresponding to different ones of the plurality of interconnect wires. The plurality of real temperatures account for Joule heating on the plurality of interconnect wires. An average current limit calculation element is configured to determine an average current limit at a first one of the plurality of actual temperatures. A comparator is configured to determine an electromigration violation on a first interconnect wire by comparing the average current limit to an average current of the first interconnect wire.

Abstract: A semiconductor device includes: a power grid (PG) arrangement including: a conductive layer M(i) including segments which are conductive, where i is an integer and i?0; and a conductive layer M(i+1) over the conductive layer M(i), the conductive layer M(i+1) including segments which are conductive; the M(i) segments including first and second segments designated correspondingly for first and second reference voltages, the first and second segments being interspersed and substantially parallel to a first direction; and the segments in the conductive layer M(i+1) including third and fourth segments designated correspondingly for the first and second reference voltages; the third and fourth segments being interspersed and substantially parallel to a perpendicular second direction; and wherein the segments in the conductive layer M(i+1) are arranged substantially asymmetrically such that each fourth segment is located, relative to the first direction, substantially asymmetrically between corresponding adjacent o

Abstract: The present disclosure, in some embodiments, relates to a method of performing electromigration sign-off. The method includes determining an environmental temperature having a same value corresponding to a plurality of interconnect wires within a plurality of electrical networks of an integrated chip design. A plurality of actual temperatures having different values corresponding to different ones of the plurality of interconnect wires are determined. The plurality of actual temperatures are respectively determined by adding the environmental temperature to a real temperature that accounts for Joule heating one of the plurality of interconnect wires. An electromigration margin for a first interconnect wire within a first electrical network of the plurality of electrical networks is determined. The electromigration margin is determined at a first one of the plurality of actual temperatures corresponding to the first interconnect wire. The electromigration margin is compared to an electromigration metric.

Abstract: A method of designing an integrated circuit device includes receiving an initial design of an integrated circuit, including a selection and location of a functional group of integrated circuit components, a power grid with multiple layers of conductive lines for supplying power to the components, and vias of one or more initial sizes interconnecting the conductive lines of different layers. The method further includes determining, based on a predetermined criterion such as the existence of unoccupied space for a functional unit, that a via modification can be made. The method further includes substituting the one or more of the via with a modified via of a larger cross-sectional area or a plurality of vias having a larger total cross-sectional area than the initial via. The method further includes confirming that the modified design complies with a predetermined set of design rules.

Abstract: A method performed by at least one processor includes: accessing a layout of an integrated circuit (IC), the layout comprising a resistor-capacitor (RC) netlist comprising a plurality of circuit nodes; identifying an RC network in the RC netlist; determining a characterization matrix corresponding to the RC network; updating the RC netlist by replacing the RC network with the characterization matrix; and calculating voltages and currents of the plurality of circuit nodes based on the updated RC netlist.

Abstract: A FIT evaluation method for an IC is provided. The FIT evaluation method includes accessing data representing a layout of the IC comprising a number of metal lines and a number of VIAs; picking a number of nodes along the metal lines; dividing each of the metal lines into a number of metal segments based on the nodes; and determining a FIT value for each of the metal segments or VIAs to verify the layout and fabricate the IC.