Abstract: A system for simulating reliability of a circuit design includes: a first memory device, arranged to store a technology file, wherein the circuit design comprises a plurality of circuit cells, and the first memory device further stores a plurality of first failure rates corresponding to a first circuit cell in the plurality of circuit cells; a first simulating device, coupled to the first memory device, for generating a first specific failure rate of the first circuit cell according to the plurality of first failure rates and the technology file; and an operating device, coupled to the first simulating device, for generating a total failure rate of the circuit design according to the first specific failure rate.

Abstract: A FIT evaluation method for an IC is provided. The FIT evaluation method includes accessing data representing a layout of the IC comprising a number of metal lines and a number of VIAs; picking a number of nodes along the metal lines; dividing each of the metal lines into a number of metal segments based on the nodes; and determining a FIT value for each of the metal segments or VIAs to verify the layout and fabricate the IC.

Abstract: A method includes receiving an input that is in an electronic file format and that includes information associated with an integrated circuit (IC) layout, selecting a non EM rule compliant metal line of the IC layout that is in violation of an EM rule from the input, obtaining a current of the non EM rule compliant metal line from the input, comparing the current with a threshold current, and determining whether the EM rule violation is negligible based on the result of comparison. As such, a semiconductor device may be fabricated from the IC layout when it is determined that the EM rule violation is negligible.

Abstract: The present disclosure, in some embodiments, relates to a method of performing electromigration sign-off. The method includes determining an environmental temperature having a same value corresponding to a plurality of interconnect wires within a plurality of electrical networks of an integrated chip design. A plurality of actual temperatures having different values corresponding to different ones of the plurality of interconnect wires are determined. The plurality of actual temperatures are respectively determined by adding the environmental temperature to a real temperature that accounts for Joule heating one of the plurality of interconnect wires. An electromigration margin for a first interconnect wire within a first electrical network of the plurality of electrical networks is determined. The electromigration margin is determined at a first one of the plurality of actual temperatures corresponding to the first interconnect wire. The electromigration margin is compared to an electromigration metric.

Abstract: The present disclosure relates to an electromigration (EM) sign-off methodology that determines EM violations of components on different electrical networks of an integrated chip design using separate temperatures. In some embodiments, the method determines a plurality of actual temperatures that respectively correspond to one or more components within one of a plurality of electrical networks within an integrated chip design. An electromigration margin is determined for a component within a selected electrical network of the plurality of electrical networks. The electromigration margin is determined at one of the plurality of actual temperatures that corresponds to the component within the selected electrical network. The electromigration margin is compared to an electromigration metric to determine if an electromigration violation of the component within the selected electrical network is present.

Abstract: An integrated circuit (IC) structure includes a power rail oriented in a power rail direction and first metal segments above the power rail, oriented in a first metal level direction perpendicular to the power rail direction. First vias positioned between the power rail and the first metal segments are positioned at locations where first metal segments overlap the power rail. A second metal segment is positioned above the first metal segments, overlaps the power rail, and is oriented in the power rail direction. Second vias are positioned above the first vias between the first metal segments and the second metal segments, and a power strap is positioned above the second metal segment. The power strap is electrically connected to the power rail, each first metal segment of the plurality of first metal segments has a minimum width, and the power strap has a width greater than a minimum width.

Abstract: A FIT evaluation method for an IC is provided. The FIT evaluation method includes accessing data representing a layout of the IC comprising a number of metal lines and a number of VIAs; picking a number of nodes along the metal lines; dividing each of the metal lines into a number of metal segments based on the nodes; and determining a FIT value for each of the metal segments or VIAs to verify the layout and fabricate the IC.

Abstract: A method includes receiving an input that is in an electronic file format and that includes information associated with an integrated circuit (IC) layout, selecting a non EM rule compliant metal line of the IC layout that is in violation of an EM rule from the input, obtaining a current of the non EM rule compliant metal line from the input, comparing the current with a threshold current, and determining whether the EM rule violation is negligible based on the result of comparison. As such, a semiconductor device may be fabricated from the IC layout when it is determined that the EM rule violation is negligible.

Abstract: Power grids of an IC are provided. A power grid includes first power traces disposed in a first metal layer and parallel to a first direction, second power traces disposed in a second metal layer and parallel to a second direction that is perpendicular to the first direction, and third power traces disposed in the first metal layer parallel to the first direction. The first power traces arranged in the same straight line are separated from each other by a plurality of first gaps. The third power traces arranged in the same straight line are separated from each other by a plurality of second gaps. Each first gap is surrounded by the two adjacent third power traces. Each second gap is surrounded by the two adjacent first power traces. The first power traces are coupled to the third power traces via the second power traces.

Abstract: A method comprises: accessing data representing a layout of a layer of an integrated circuit (IC) comprising a plurality of polygons defining circuit patterns to be divided among a number (N) of photomasks for multi-patterning a single layer of a semiconductor substrate, where N is greater than one. For each set of N parallel polygons in the layout closer to each other than a minimum separation for patterning with a single photomask, at least N?1 stitches are inserted in each polygon within that set to divide each polygon into at least N parts, such that adjacent parts of different polygons are assigned to different photomasks from each other. Data representing assignment of each of the parts in each set to respective photomasks are stored in a non-transitory, computer readable storage medium that is accessible for use in a process to fabricate the N photomasks.

Abstract: A method of determining electromigration (EM) compliance of a circuit is performed. The method includes providing a layout of the circuit, the layout comprising one or more metal lines, and changing a property of one or more of the one or more metal lines within one or more nets of a plurality of nets in the layout. Each of the nets includes a subset of the one or more metal lines. The method also includes determining one or more current values drawn only within the one or more nets and comparing the determined one or more current values drawn with corresponding threshold values. Based on the comparison, an indication is provided whether or not the layout is compliant. A pattern of the one or more metal lines in the compliant layout is transferred to a mask to be used in the manufacturing of the circuit on a substrate.

Abstract: The present disclosure relates to an electromigration (EM) sign-off methodology that determines EM violations of components on different electrical networks of an integrated chip design using separate temperatures. In some embodiments, the method determines a plurality of actual temperatures that respectively correspond to one or more components within one of a plurality of electrical networks within an integrated chip design. An electromigration margin is determined for a component within a selected electrical network of the plurality of electrical networks. The electromigration margin is determined at one of the plurality of actual temperatures that corresponds to the component within the selected electrical network. The electromigration margin is compared to an electromigration metric to determine if an electromigration violation of the component within the selected electrical network is present.

Abstract: A circuit is disclosed that includes a plurality of voltage control circuits and a control module. Each of the voltage control circuits is controlled by a control signal. The control module is configured to generate the control signal and to determine a voltage level or a pulse width of the control signal in accordance with a current process corner condition of the voltage control circuits and at least one of first predetermined data and second predetermined data.

Abstract: A circuit is disclosed that includes a plurality of voltage control circuits. Each voltage control circuit of the voltage control circuits includes a driver circuit and a switch circuit. The driver circuit is configured to receive a control signal having a series of pulses. The switch circuit is configured to generate a driving voltage when being turned on. The driver circuit alternately turns on and off the switch circuit in accordance with the series of pulses.

Abstract: In some embodiments, in a method, placement of a design layout is performed. The design layout includes a power rail segment, several upper-level power lines and several cells. The upper-level power lines cross over and bound the power rail segment at where the upper-level power lines intersect with the power rail segment. The cells are powered through the power rail segment. For each cell, a respective current through the power rail segment during a respective SW of the cell is obtained. One or more groups of cells with overlapped SWs are determined. One or more EM usages of the power rail segment by the one or more groups of cells using the respective currents of each group of cells are obtained. The design layout is adjusted when any of the one or more EM usages of the power rail segment causes an EM susceptibility of the power rail segment.

Abstract: A method comprises: accessing data representing a layout of a layer of an integrated circuit (IC) comprising a plurality of polygons defining circuit patterns to be divided among a number (N) of photomasks for multi-patterning a single layer of a semiconductor substrate, where N is greater than one. For each set of N parallel polygons in the layout closer to each other than a minimum separation for patterning with a single photomask, at least N?1 stitches are inserted in each polygon within that set to divide each polygon into at least N parts, such that adjacent parts of different polygons are assigned to different photomasks from each other. Data representing assignment of each of the parts in each set to respective photomasks are stored in a non-transitory, computer readable storage medium that is accessible for use in a process to fabricate the N photomasks.

Abstract: A method is disclosed that includes the operations outlined below. A first criteria is determined to be met when directions of a first current and a second current around a first end and a second end of a metal segment respectively are opposite, in which the metal segment is a part of a power rail in at least one design file of a semiconductor device and is enclosed by only two terminal via arrays. A second criteria is determined to be met when a length of the metal segment is not larger than a electromigration critical length. The metal segment is included in the semiconductor device with a first current density limit depending on the length of the metal segment when the first and the second criteria are met.

Abstract: In some embodiments, in a method, cell layouts of a plurality of cells are received. For each cell, a respective constraint that affects a geometry of an interconnect to be coupled to an output pin of the cell in a design layout is determined based on a geometry of the output pin of the cell in the cell layout.

Abstract: A method comprises: accessing data representing a layout of a layer of an integrated circuit (IC) comprising a plurality of polygons defining circuit patterns to be divided among a number (N) of photomasks for multi-patterning a single layer of a semiconductor substrate, where N is greater than one. For each set of N parallel polygons in the layout closer to each other than a minimum separation for patterning with a single photomask, at least N?1 stitches are inserted in each polygon within that set to divide each polygon into at least N parts, such that adjacent parts of different polygons are assigned to different photomasks from each other. Data representing assignment of each of the parts in each set to respective photomasks are stored in a non-transitory, computer readable storage medium that is accessible for use in a process to fabricate the N photomasks.

Abstract: A method is disclosed that includes the operations outlined below. A first criteria is determined to be met when directions of a first current and a second current around a first end and a second end of a metal segment respectively are opposite, in which the metal segment is a part of a power rail in at least one design file of a semiconductor device and is enclosed by only two terminal via arrays. A second criteria is determined to be met when a length of the metal segment is not larger than a electromigration critical length. The metal segment is included in the semiconductor device with a first current density limit depending on the length of the metal segment when the first and the second criteria are met.