Patents by Inventor Chin-Sheng Wang
Chin-Sheng Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9870931Abstract: A package carrier includes a substrate, at least one heat conducting element, an insulating material, a first patterned circuit layer and a second patterned circuit layer. The substrate has an upper surface, a lower surface and a through hole. The heat conducting element is disposed inside the through hole and has a first surface and a second surface. The insulating material has a top surface, a bottom surface and at least one cavity extending from the top surface to the heat conducting element. The heat conducting element is fixed in the through hole by the insulating material, and the cavity exposes a portion of the first surface of the heat conducting element. The first patterned circuit layer is disposed on the upper surface and the top surface, and the second patterned circuit layer is disposed on the lower surface and the bottom surface.Type: GrantFiled: January 19, 2016Date of Patent: January 16, 2018Assignee: Subtron Technology Co., Ltd.Inventors: Chin-Sheng Wang, Shih-Hao Sun
-
Publication number: 20170325330Abstract: A manufacturing method of a circuit substrate includes the following steps. A core layer having a core dielectric layer, a first patterned circuit layer and a second patterned circuit layer is provided. An electroless plating nickel layer is formed on the first patterned circuit layer and the second patterned circuit layer. The electroless plating nickel layer has a first thickness, and the first thickness is between 1 micrometer and 10 micrometers. A reducing process is performed on the electroless plating nickel layer so that the electroless plating nickel layer is thinned from the first thickness to a second thickness to form a thinned electroless plating nickel layer. The second thickness is between 0.01 micrometers and 0.9 micrometers. An electroless plating palladium layer is formed on the thinned electroless plating nickel layer. A surface metal passivation layer is formed on the electroless plating palladium layer.Type: ApplicationFiled: June 7, 2016Publication date: November 9, 2017Inventors: Chin-Sheng Wang, Ching-Sheng Chen, Ching-Ta Chen, Mei-Chin Chang
-
Publication number: 20170079128Abstract: A package carrier includes a substrate, at least one heat conducting element, an insulating material, a first patterned circuit layer and a second patterned circuit layer. The substrate has an upper surface, a lower surface and a through hole. The heat conducting element is disposed inside the through hole and has a first surface and a second surface. The insulating material has a top surface, a bottom surface and at least one cavity extending from the top surface to the heat conducting element. The heat conducting element is fixed in the through hole by the insulating material, and the cavity exposes a portion of the first surface of the heat conducting element. The first patterned circuit layer is disposed on the upper surface and the top surface, and the second patterned circuit layer is disposed on the lower surface and the bottom surface.Type: ApplicationFiled: January 19, 2016Publication date: March 16, 2017Inventors: Chin-Sheng Wang, Shih-Hao Sun
-
Patent number: 9591753Abstract: A circuit board includes a substrate, a patterned copper layer, a phosphorous-containing electroless plating palladium layer, an electroless plating palladium layer and an immersion plating gold layer. The patterned copper layer is disposed on the substrate. The phosphorous-containing electroless plating palladium layer is disposed on the patterned copper layer, wherein in the phosphorous-containing electroless plating palladium layer, a weight percentage of phosphorous is in a range from 4% to 6%, and a weight percentage of palladium is in a range from 94% to 96%. The electroless plating palladium layer is disposed on the phosphorous-containing electroless plating palladium layer, wherein in the electroless plating palladium layer, a weight percentage of palladium is 99% or more. The immersion plating gold layer is disposed on the electroless plating palladium layer.Type: GrantFiled: September 10, 2015Date of Patent: March 7, 2017Assignee: Subtron Technology Co., Ltd.Inventors: Chin-Sheng Wang, Ching-Sheng Chen, Mei-Chin Chang, Ching-Ta Chen
-
Publication number: 20170013710Abstract: A circuit board includes a substrate, a patterned copper layer, a phosphorous-containing electroless plating palladium layer, an electroless plating palladium layer and an immersion plating gold layer. The patterned copper layer is disposed on the substrate. The phosphorous-containing electroless plating palladium layer is disposed on the patterned copper layer, wherein in the phosphorous-containing electroless plating palladium layer, a weight percentage of phosphorous is in a range from 4% to 6%, and a weight percentage of palladium is in a range from 94% to 96%. The electroless plating palladium layer is disposed on the phosphorous-containing electroless plating palladium layer, wherein in the electroless plating palladium layer, a weight percentage of palladium is 99% or more. The immersion plating gold layer is disposed on the electroless plating palladium layer.Type: ApplicationFiled: September 10, 2015Publication date: January 12, 2017Inventors: Chin-Sheng Wang, Ching-Sheng Chen, Mei-Chin Chang, Ching-Ta Chen
-
Patent number: 9458540Abstract: A manufacturing method of a package substrate is provided. A first base is formed. Metal bumps are formed on the first base by plating. A second base having an upper and a lower surfaces, a core dielectric layer, a first and a second copper foil layers and containing cavities is provided. An adhesive layer is formed on inner walls of the containing cavities. The first and the second bases are laminated so that the metal bumps are disposed inside the containing cavities. A first base is removed. Blind via holes extending from the upper surface to the metal bumps are formed. A conductive material layer is formed on the first and the second copper foil layers, wherein the conductive material layer fills the blind via holes so as to define conductive through via holes. The conductive material layer is patterned to form a first and a second patterned metal layers.Type: GrantFiled: April 14, 2015Date of Patent: October 4, 2016Assignee: Subtron Technology Co., Ltd.Inventors: Chin-Sheng Wang, Chien-Ming Chen
-
Patent number: 9433099Abstract: A package carrier including a removable supporting plate and a circuit board is provided. The removable supporting plate includes a dielectric layer, a copper foil layer and a releasing layer. The dielectric layer is disposed between the copper foil layer and the releasing layer. The circuit board is disposed on the removable supporting plate and directly contacts the releasing layer. A thickness of the circuit board is between 30 ?m and 100 ?m.Type: GrantFiled: November 6, 2013Date of Patent: August 30, 2016Assignee: Subtron Technology Co., Ltd.Inventors: Chin-Sheng Wang, Ching-Sheng Chen, Chao-Min Wang
-
Publication number: 20160230286Abstract: A manufacturing method of a package substrate is provided. A first base is formed. Metal bumps are formed on the first base by plating. A second base having an upper and a lower surfaces, a core dielectric layer, a first and a second copper foil layers and containing cavities is provided. An adhesive layer is formed on inner walls of the containing cavities. The first and the second bases are laminated so that the metal bumps are disposed inside the containing cavities. A first base is removed. Blind via holes extending from the upper surface to the metal bumps are formed. A conductive material layer is formed on the first and the second copper foil layers, wherein the conductive material layer fills the blind via holes so as to define conductive through via holes. The conductive material layer is patterned to form a first and a second patterned metal layers.Type: ApplicationFiled: April 14, 2015Publication date: August 11, 2016Inventors: Chin-Sheng Wang, Chien-Ming Chen
-
Patent number: 9282643Abstract: A core substrate includes a dielectric layer, at least one releasing layer, at least one first copper foil layer and at least one nickel layer. The releasing layer is disposed on the dielectric layer and directly covers the dielectric layer. The first copper foil layer is disposed on the releasing layer and directly covers the releasing layer. The nickel layer is disposed on the first copper foil layer and directly covers the first copper foil layer.Type: GrantFiled: March 7, 2014Date of Patent: March 8, 2016Assignee: Subtron Technology Co., Ltd.Inventors: Chin-Sheng Wang, Chao-Min Wang
-
Patent number: 9204546Abstract: A circuit board includes a circuit layer, a first solder resist layer, a second solder resist layer and at least one conductive bump. The first solder resist layer is disposed on a lower surface of the circuit layer and has at least one first opening exposing a portion of the lower surface of the circuit layer. The second solder resist layer is disposed on an upper surface of the circuit layer and has at least one second opening exposing a portion of the upper surface of the circuit layer. The conductive bump is disposed inside the second opening of the second solder resist layer and directly connects to the upper surface of the circuit layer exposed by the second opening. A top surface of the conductive bump is higher than a second surface of the second solder resist layer.Type: GrantFiled: February 17, 2014Date of Patent: December 1, 2015Assignee: Subtron Technology Co., Ltd.Inventors: Chin-Sheng Wang, Ching-Sheng Chen, Chun-Kai Lin, Chao-Min Wang
-
Publication number: 20150195917Abstract: A core substrate includes a dielectric layer, at least one releasing layer, at least one first copper foil layer and at least one nickel layer. The releasing layer is disposed on the dielectric layer and directly covers the dielectric layer. The first copper foil layer is disposed on the releasing layer and directly covers the releasing layer. The nickel layer is disposed on the first copper foil layer and directly covers the first copper foil layer.Type: ApplicationFiled: March 7, 2014Publication date: July 9, 2015Applicant: Subtron Technology Co., Ltd.Inventors: Chin-Sheng Wang, Chao-Min Wang
-
Publication number: 20150163908Abstract: A circuit board includes a circuit layer, a first solder resist layer, a second solder resist layer and at least one conductive bump. The first solder resist layer is disposed on a lower surface of the circuit layer and has at least one first opening exposing a portion of the lower surface of the circuit layer. The second solder resist layer is disposed on an upper surface of the circuit layer and has at least one second opening exposing a portion of the upper surface of the circuit layer. The conductive bump is disposed inside the second opening of the second solder resist layer and directly connects to the upper surface of the circuit layer exposed by the second opening. A top surface of the conductive bump is higher than a second surface of the second solder resist layer.Type: ApplicationFiled: February 17, 2014Publication date: June 11, 2015Applicant: SUBTRON TECHNOLOGY CO., LTD.Inventors: Chin-Sheng Wang, Ching-Sheng Chen, Chun-Kai Lin, Chao-Min Wang
-
Publication number: 20150114698Abstract: A substrate structure includes a substrate and a filling material. The substrate has an upper surface, a lower surface, at least one first blind via and at least one second blind via. The substrate includes an insulation layer, a first copper foil layer and a second copper foil layer. The first copper foil layer and the second copper foil layer are respectively disposed on two opposite side surfaces of the insulation layer. The first blind via extends from the upper surface toward the second copper foil layer and exposes a portion of the second copper foil layer. The second blind via extends from the lower surface toward the first copper foil layer and exposes a portion of the first copper foil layer. The filling material is filled inside of the first blind via and the second blind via and covers the upper surface and the lower surface of the substrate.Type: ApplicationFiled: December 13, 2013Publication date: April 30, 2015Applicant: SUBTRON TECHNOLOGY CO., LTD.Inventors: Tzu-Wei Huang, Chin-Sheng Wang
-
Patent number: 9008736Abstract: The invention relates to a protective frame for a mobile communication device having a power charging port. The protective frame has a retractable frame body, including a main frame body; a sliding element for reciprocatingly sliding along a direction with respect to the main frame body between a retracted protection position where the mobile communication device is fixedly framed by the retractable frame body and a stretched auxiliary power supply position; and a fastening element for fixing the sliding element with respect to the main frame body at the retracted protection position and the stretched auxiliary power supply position. The protective frame also includes an auxiliary battery adapted for being detachably installed in the retractable frame body and electrically connected to the power charging port of the mobile communication device, when the sliding element are fixed with respect to the main frame body at the stretched auxiliary power supply position.Type: GrantFiled: December 8, 2013Date of Patent: April 14, 2015Assignee: Taer Innovation Co., Ltd.Inventors: Li-Ming Hu, Yu-Chun Lu, Chin-Sheng Wang
-
Publication number: 20150092358Abstract: A package carrier including a removable supporting plate and a circuit board is provided. The removable supporting plate includes a dielectric layer, a copper foil layer and a releasing layer. The dielectric layer is disposed between the copper foil layer and the releasing layer. The circuit board is disposed on the removable supporting plate and directly contacts the releasing layer. A thickness of the circuit board is between 30 ?m and 100 ?m.Type: ApplicationFiled: November 6, 2013Publication date: April 2, 2015Applicant: SUBTRON TECHNOLOGY CO., LTD.Inventors: Chin-Sheng Wang, Ching-Sheng Chen, Chao-Min Wang
-
Patent number: 8859908Abstract: A package carrier includes a substrate, first and second insulation layers, first and second patterned circuit layers, at least one first and second conductive through holes, a heat dissipation channel, an adhesive layer and a heat conducting element. The first and second patterned circuit layers are respectively disposed on the first and second insulation layers which are respectively disposed on upper and lower surfaces of the substrate. The heat dissipation channel at least passes through the first insulation layer, the first and second patterned circuit layers, and the substrate. The first and second conductive through holes electrically connect with the substrate, the first and second patterned circuit layers. At least two opposite side surfaces of the heat conducting element each includes at least one convex portion or at least one concave portion. The heat conducting element is mounted in the heat dissipation channel via the adhesive layer.Type: GrantFiled: February 26, 2013Date of Patent: October 14, 2014Assignee: Subtron Technology Co., Ltd.Inventors: Chin-Sheng Wang, Chien-Ming Chen
-
Publication number: 20140144677Abstract: A package carrier includes a substrate, first and second insulation layers, first and second patterned circuit layers, at least one first and second conductive through holes, a heat dissipation channel, an adhesive layer and a heat conducting element. The first and second patterned circuit layers are respectively disposed on the first and second insulation layers which are respectively disposed on upper and lower surfaces of the substrate. The heat dissipation channel at least passes through the first insulation layer, the first and second patterned circuit layers, and the substrate. The first and second conductive through holes electrically connect with the substrate, the first and second patterned circuit layers. At least two opposite side surfaces of the heat conducting element each includes at least one convex portion or at least one concave portion. The heat conducting element is mounted in the heat dissipation channel via the adhesive layer.Type: ApplicationFiled: February 26, 2013Publication date: May 29, 2014Applicant: Subtron Technology Co., Ltd.Inventors: Chin-Sheng Wang, Chien-Ming Chen
-
Publication number: 20140094227Abstract: The invention relates to a protective frame for a mobile communication device having a power charging port. The protective frame has a retractable frame body, including a main frame body; a sliding element for reciprocatingly sliding along a direction with respect to the main frame body between a retracted protection position where the mobile communication device is fixedly framed by the retractable frame body and a stretched auxiliary power supply position; and a fastening element for fixing the sliding element with respect to the main frame body at the retracted protection position and the stretched auxiliary power supply position. The protective frame also includes an auxiliary battery adapted for being detachably installed in the retractable frame body and electrically connected to the power charging port of the mobile communication device, when the sliding element are fixed with respect to the main frame body at the stretched auxiliary power supply position.Type: ApplicationFiled: December 8, 2013Publication date: April 3, 2014Applicant: CORE DESIGN COMMUNICATION LTD.Inventors: Li-Ming Hu, Yu-Chun Lu, Chin-Sheng Wang
-
Patent number: D712385Type: GrantFiled: May 1, 2012Date of Patent: September 2, 2014Assignee: Taer Innovation Co., Ltd.Inventors: Li-Ming Hu, Yu-Chun Lu, Chin-Sheng Wang
-
Patent number: D722952Type: GrantFiled: March 19, 2013Date of Patent: February 24, 2015Assignee: Taer Innovation Co., Ltd.Inventors: Li-Ming Hu, Yu-Chun Lu, Chin-Sheng Wang, Shih-Chin Huang, Chun-Wei Tseng