Patents by Inventor Chin-Wei Kuo
Chin-Wei Kuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20160358871Abstract: An integrated circuit package includes a die. An electrically conductive layer comprises a redistribution layer (RDL) in the die, or a micro-bump layer above the die, or both. The micro bump layer comprises at least one micro-bump line. A filter comprises the electrically conductive layer. A capacitor comprises an electrode formed in the electrically conductive layer.Type: ApplicationFiled: August 16, 2016Publication date: December 8, 2016Inventors: Hsiao-Tsung Yen, Jhe-Ching Lu, Yu-Ling Lin, Chin-Wei Kuo, Min-Chie Jeng
-
Patent number: 9472612Abstract: A method includes forming first, second, and third conductive leaf structures. The first conductive leaf structure includes a first conductive midrib and conductive veins. The second conductive leaf structure is electrically connected to the first conductive leaf structure, and includes a second conductive midrib, conductive veins extending toward the first conductive midrib, and conductive veins extending away from the first conductive midrib. The third conductive leaf structure includes a third conductive midrib between the first conductive midrib and the second conductive midrib, conductive veins extending toward the first conductive midrib, and conductive veins extending toward the second conductive midrib.Type: GrantFiled: March 15, 2016Date of Patent: October 18, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chin-Wei Kuo, Cheng-Wei Luo, Hsiao-Tsung Yen, Jun-Cheng Huang, Min-Chie Jeng
-
Patent number: 9449917Abstract: In accordance with an embodiment, a semiconductor device comprises a semiconductor die, an interposer, and conductive bumps bonding the semiconductor die to the interposer. The semiconductor die comprises a first metallization layer, and the first metallization layer comprises a first conductive pattern. The interposer comprises a second metallization layer, and the second metallization layer comprises a second conductive pattern. Some of the conductive bumps electrically couple the first conductive pattern to the second conductive pattern to form a coil. A magnetic layer is positioned within the coil. In another embodiment, a coil is formed on a single substrate, wherein a magnetic layer is positioned within the coil. Other embodiments contemplate other configurations of coils, inductors, and/or transformers, and contemplate methods of manufacture.Type: GrantFiled: May 24, 2015Date of Patent: September 20, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Wei Luo, Hsiao-Tsung Yen, Chin-Wei Kuo, Min-Chie Jeng
-
Patent number: 9449945Abstract: An integrated circuit package includes a die. An electrically conductive layer comprises a redistribution layer (RDL) in the die, or a micro-bump layer above the die, or both. The micro bump layer comprises at least one micro-bump line. A filter comprises the electrically conductive layer. A capacitor comprises an electrode formed in the electrically conductive layer.Type: GrantFiled: March 8, 2013Date of Patent: September 20, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsiao-Tsung Yen, Jhe-Ching Lu, Yu-Ling Yu, Chin-Wei Kuo, Min-Chie Jeng
-
Publication number: 20160197137Abstract: A method includes forming first, second, and third conductive leaf structures. The first conductive leaf structure includes a first conductive midrib and conductive veins. The second conductive leaf structure is electrically connected to the first conductive leaf structure, and includes a second conductive midrib, conductive veins extending toward the first conductive midrib, and conductive veins extending away from the first conductive midrib. The third conductive leaf structure includes a third conductive midrib between the first conductive midrib and the second conductive midrib, conductive veins extending toward the first conductive midrib, and conductive veins extending toward the second conductive midrib.Type: ApplicationFiled: March 15, 2016Publication date: July 7, 2016Inventors: Chin-Wei Kuo, Cheng-Wei Luo, Hsiao-Tsung Yen, Jun-Cheng Huang, Min-Chie Jeng
-
Patent number: 9385246Abstract: A differential MOS capacitor includes a first plurality of upper capacitor plates, a second plurality of upper capacitor plates, and a conductive plate. At least two of the second plurality of upper capacitor plates are spaced laterally from each other and are disposed laterally between at least two of the first plurality of upper capacitor plates. The conductive plate is configured to serve as a common bottom capacitor plate such that a first capacitor is formed by the first plurality of upper capacitor plates and the conductive plate and a second capacitor is formed by the second plurality of upper capacitor plates and the conductive plate.Type: GrantFiled: January 12, 2015Date of Patent: July 5, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsiao-Tsung Yen, Yu-Ling Lin, Chin-Wei Kuo, Min-Chie Jeng
-
Patent number: 9373673Abstract: In accordance with an embodiment, a semiconductor device comprises a semiconductor die, an interposer, and conductive bumps bonding the semiconductor die to the interposer. The semiconductor die comprises a first metallization layer, and the first metallization layer comprises a first conductive pattern. The interposer comprises a second metallization layer, and the second metallization layer comprises a second conductive pattern. Some of the conductive bumps electrically couple the first conductive pattern to the second conductive pattern to form a coil. Other embodiments contemplate other configurations of coils, inductors, and/or transformers, and contemplate methods of manufacture.Type: GrantFiled: May 21, 2015Date of Patent: June 21, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsiao-Tsung Yen, Chin-Wei Kuo, Hsien-Pin Hu, Sally Liu, Ming-Fa Chen, Jhe-Ching Lu
-
Patent number: 9331013Abstract: A structure includes first, second, and third conductive leaf structures. The first conductive leaf structure includes a first conductive midrib and conductive veins. The second conductive leaf structure is electrically connected to the first conductive leaf structure, and includes a second conductive midrib, conductive veins extending toward the first conductive midrib, and conductive veins extending away from the first conductive midrib. The third conductive leaf structure includes a third conductive midrib between the first conductive midrib and the second conductive midrib, conductive veins extending toward the first conductive midrib, and conductive veins extending toward the second conductive midrib.Type: GrantFiled: May 24, 2013Date of Patent: May 3, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsiao-Tsung Yen, Cheng-Wei Luo, Jun-Cheng Huang, Chin-Wei Kuo, Min-Chie Jeng
-
Publication number: 20160027750Abstract: Methods and apparatus for forming a semiconductor device package with a transmission line using a micro-bump layer are disclosed. The micro-bump layer may comprise micro-bumps and micro-bump lines, formed between a top device and a bottom device. A signal transmission line may be formed using a micro-bump line above a bottom device. A ground plane may be formed using a redistribution layer (RDL) within the bottom device, or using additional micro-bump lines. The RDL formed ground plane may comprise open slots. There may be RDLs at the bottom device and the top device above and below the micro-bump lines to form parts of the ground planes.Type: ApplicationFiled: October 5, 2015Publication date: January 28, 2016Inventors: Chin-Wei Kuo, Hsiao-Tsung Yen, Min-Chie Jeng, Yu-Ling Lin
-
Patent number: 9203146Abstract: An antenna includes a substrate and a conductive top plate over the substrate. A feed line is connected to the top plate, and the feed line comprises a first through-silicon via (TSV) structure passing through the substrate. The feed line is arranged to carry a radio frequency signal. A method of designing an antenna includes selecting a shape of a top plate, determining a size of the top plate based on an intended signal frequency, and determining, based on the shape of the top plate, a location of each TSV of at least one TSV contacting the top plate. A method of implementing an antenna includes forming a first feed line through a substrate, the first feed line comprising a TSV, and forming a top plate over the substrate, the top plate being electrically conductive and connected to the first feed line.Type: GrantFiled: February 5, 2014Date of Patent: December 1, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsiao-Tsung Yen, Jhe-Ching Lu, Yu-Ling Lin, Chin-Wei Kuo, Min-Chie Jeng
-
Publication number: 20150325517Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate having an integrated circuit (IC) device; an interconnect structure disposed on the semiconductor substrate and coupled with the IC device; and a transformer disposed on the semiconductor substrate and integrated in the interconnect structure. The transformer includes a first conductive feature; a second conductive feature inductively coupled with the first conductive feature; a third conductive feature electrically connected to the first conductive feature; and a fourth conductive feature electrically connected to the second conductive feature. The third and fourth conductive features are designed and configured to be capacitively coupled to increase a coupling coefficient of the transformer.Type: ApplicationFiled: July 20, 2015Publication date: November 12, 2015Inventors: Hsiao-Tsung Yen, Chin-Wei Kuo, Ho-Hsiang Chen, Min-Chie Jeng, Yu-Ling Lin
-
Publication number: 20150325513Abstract: A strip-line includes a ground plane extending through a plurality of dielectric layers over a substrate; a signal line over the substrate and on a side of the ground plane; a first plurality of metal strips under the signal line and in a first metal layer, wherein the first plurality of metal strips is parallel to each other, and is spaced apart from each other by spaces; and a second plurality of metal strips under the signal line and in a second metal layer over the first metal layer. The second plurality of metal strips vertically overlaps the spaces. The first plurality of metal strips is electrically coupled to the second plurality of metal strips through the ground plane, and no via physically contacts the first plurality of metal strips and the second plurality of metal strips.Type: ApplicationFiled: July 17, 2015Publication date: November 12, 2015Inventors: Yu-Ling Lin, Hsiao-Tsung Yen, Ho-Hsiang Chen, Chin-Wei Kuo, Chewn-Pu Jou
-
Publication number: 20150316603Abstract: An apparatus includes three components. The first component includes a first transmission line; the second component is coupled with the first component and includes a second transmission line; and the third component electrically coupled with the first component and/or the second component. The transmission lines each include a substrate with a p-well or n-well within the substrate and a shielding layer over the p-well or n-well. The transmission lines also each include a plurality of intermediate conducting layers over the shielding layer, the plurality of intermediate conducting layers coupled by a plurality of vias. The transmission lines further each include a top conducting layer over the plurality of intermediate conducting layers.Type: ApplicationFiled: July 14, 2015Publication date: November 5, 2015Inventors: Hsiao-Tsung Yen, Chin-Wei Kuo, Ho-Hsiang Chen, Sa-Lly Liu, Yu-Ling Lin
-
Patent number: 9171798Abstract: Methods and apparatus for forming a semiconductor device package with a transmission line using a micro-bump layer are disclosed. The micro-bump layer may comprise micro-bumps and micro-bump lines, formed between a top device and a bottom device. A signal transmission line may be formed using a micro-bump line above a bottom device. A ground plane may be formed using a redistribution layer (RDL) within the bottom device, or using additional micro-bump lines. The RDL formed ground plane may comprise open slots. There may be RDLs at the bottom device and the top device above and below the micro-bump lines to form parts of the ground planes.Type: GrantFiled: January 25, 2013Date of Patent: October 27, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Ling Lin, Hsiao-Tsung Yen, Chin-Wei Kuo, Min-Chie Jeng
-
Patent number: 9147020Abstract: A method includes simulating characteristics of a first transmission line having a first length, and simulating characteristics of a second transmission line having a second length greater than the first length. A calculation is then performed on the characteristics of the first transmission line and the characteristics of the second transmission line to generate intrinsic characteristics of a third transmission line having a length equal to a difference of the second length and the first length.Type: GrantFiled: April 21, 2011Date of Patent: September 29, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsiu-Ying Cho, Jiun-Kai Huang, Wen-Sheh Huang, Chin-Wei Kuo, Min-Chie Jeng
-
Publication number: 20150255531Abstract: In accordance with an embodiment, a semiconductor device comprises a semiconductor die, an interposer, and conductive bumps bonding the semiconductor die to the interposer. The semiconductor die comprises a first metallization layer, and the first metallization layer comprises a first conductive pattern. The interposer comprises a second metallization layer, and the second metallization layer comprises a second conductive pattern. Some of the conductive bumps electrically couple the first conductive pattern to the second conductive pattern to form a coil. Other embodiments contemplate other configurations of coils, inductors, and/or transformers, and contemplate methods of manufacture.Type: ApplicationFiled: May 21, 2015Publication date: September 10, 2015Inventors: Hsiao-Tsung Yen, Chin-Wei Kuo, Hsien-Pin Hu, Sally Liu, Ming-Fa Chen, Jhe-Ching Lu
-
Publication number: 20150255391Abstract: In accordance with an embodiment, a semiconductor device comprises a semiconductor die, an interposer, and conductive bumps bonding the semiconductor die to the interposer. The semiconductor die comprises a first metallization layer, and the first metallization layer comprises a first conductive pattern. The interposer comprises a second metallization layer, and the second metallization layer comprises a second conductive pattern. Some of the conductive bumps electrically couple the first conductive pattern to the second conductive pattern to form a coil. A magnetic layer is positioned within the coil. In another embodiment, a coil is formed on a single substrate, wherein a magnetic layer is positioned within the coil. Other embodiments contemplate other configurations of coils, inductors, and/or transformers, and contemplate methods of manufacture.Type: ApplicationFiled: May 24, 2015Publication date: September 10, 2015Inventors: Cheng-Wei Luo, Hsiao-Tsung Yen, Chin-Wei Kuo, Min-Chie Jeng
-
Patent number: 9121891Abstract: An apparatus for de-embedding through substrate vias is provided. The apparatus may include pads on a first side of a substrate are coupled to through vias extending through a substrate, wherein pairs of the through vias are interconnected by transmission lines of varying lengths along a second side of the substrate. The apparatus may further include pairs of pads coupled together by transmission lines of the same varying lengths. Apparatuses may include through vias surrounding a through via device under test. The surrounding through vias are connected to the through via device under test by a backside metal layer. The apparatus may further include a dummy structure having an area equal to an area of the backside metal layer.Type: GrantFiled: July 15, 2014Date of Patent: September 1, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsiao-Tsung Yen, Min-Chie Jeng, Victor Chih Yuan Chang, Chin-Wei Kuo, Yu-Ling Lin
-
Patent number: 9103884Abstract: A transmission line is provided. In one embodiment, the transmission line comprises a substrate, a well within the substrate, a shielding layer over the well, and a plurality of intermediate metal layers over the shielding layer, the plurality of intermediate metal layers coupled by a plurality of vias. The transmission line further includes a top metal layer over the plurality of intermediate metal layers. A test structure for de-embedding an on-wafer device, and a wafer are also disclosed.Type: GrantFiled: December 8, 2010Date of Patent: August 11, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsiao-Tsung Yen, Yu-Ling Lin, Chin-Wei Kuo, Ho-Hsiang Chen, Sa-Lly Liu
-
Patent number: 9087838Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate having an integrated circuit (IC) device; an interconnect structure disposed on the semiconductor substrate and coupled with the IC device; and a transformer disposed on the semiconductor substrate and integrated in the interconnect structure. The transformer includes a first conductive feature; a second conductive feature inductively coupled with the first conductive feature; a third conductive feature electrically connected to the first conductive feature; and a fourth conductive feature electrically connected to the second conductive feature. The third and fourth conductive features are designed and configured to be capacitively coupled to increase a coupling coefficient of the transformer.Type: GrantFiled: October 25, 2011Date of Patent: July 21, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsiao-Tsung Yen, Yu-Ling Lin, Chin-Wei Kuo, Ho-Hsiang Chen, Min-Chie Jeng