Patents by Inventor Ching-Hua Chiu
Ching-Hua Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11955460Abstract: In accordance with some embodiments, a package-on-package (PoP) structure includes a first semiconductor package having a first side and a second side opposing the first side, a second semiconductor package having a first side and a second side opposing the first side, and a plurality of inter-package connector coupled between the first side of the first semiconductor package and the first side of the second semiconductor package. The PoP structure further includes a first molding material on the second side of the first semiconductor package. The second side of the second semiconductor package is substantially free of the first molding material.Type: GrantFiled: October 5, 2020Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Da Tsai, Meng-Tse Chen, Sheng-Feng Weng, Sheng-Hsiang Chiu, Wei-Hung Lin, Ming-Da Cheng, Ching-Hua Hsieh, Chung-Shi Liu
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Publication number: 20240107682Abstract: An embodiment composite material for semiconductor package mount applications may include a first component including a tin-silver-copper alloy and a second component including a tin-bismuth alloy or a tin-indium alloy. The composite material may form a reflowed bonding material having a room temperature tensile strength in a range from 80 MPa to 100 MPa when subjected to a reflow process. The reflowed bonding material may include a weight fraction of bismuth that is in a range from approximately 4% to approximately 15%. The reflowed bonding material may an alloy that is solid solution strengthened by a presence of bismuth or indium that is dissolved within the reflowed bonding material or a solid solution phase that includes a minor component of bismuth dissolved within a major component of tin. In some embodiments, the reflowed bonding material may include intermetallic compounds formed as precipitates such as Ag3Sn and/or Cu6Sn5.Type: ApplicationFiled: April 21, 2023Publication date: March 28, 2024Inventors: Chao-Wei Chiu, Chih-Chiang Tsao, Jen-Jui Yu, Hsuan-Ting Kuo, Hsiu-Jen Lin, Ching-Hua Hsieh
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Publication number: 20240096740Abstract: Provided is a package structure including a first redistribution layer (RDL) structure, a die, a circuit substrate, and a first thermoelectric cooler. The RDL) structure has a first side and a second side opposite to each other. The die is disposed on the first side of the first RDL structure. The circuit substrate is bonded to the second side of the first RDL structure through a plurality of first conductive connectors. The first thermoelectric cooler is between the first RDL structure and the circuit substrate, wherein the first thermoelectric cooler includes at least a N-type doped region and at least a P-type doped region.Type: ApplicationFiled: January 9, 2023Publication date: March 21, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chao-Wei Chiu, Chao-Wei Li, Hsiu-Jen Lin, Ching-Hua Hsieh
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Publication number: 20240071952Abstract: A method includes depositing solder paste over first contact pads of a first package component. Spring connectors of a second package component are aligned to the solder paste. The solder paste is reflowed to electrically and physically couple the spring connectors of the second package component to the first contact pads of the first package component. A device includes a first package component and a second package component electrically and physically coupled to the first package component by way of a plurality of spring coils. Each of the plurality of spring coils extends from the first package component to the second package component.Type: ApplicationFiled: January 10, 2023Publication date: February 29, 2024Inventors: Chih-Chiang Tsao, Hsuan-Ting Kuo, Chao-Wei Chiu, Hsiu-Jen Lin, Ching-Hua Hsieh
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Publication number: 20240071954Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.Type: ApplicationFiled: November 9, 2023Publication date: February 29, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kai-Ming Chiang, Chao-wei Li, Wei-Lun Tsai, Chia-Min Lin, Yi-Da Tsai, Sheng-Feng Weng, Yu-Hao Chen, Sheng-Hsiang Chiu, Chih-Wei Lin, Ching-Hua Hsieh
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Publication number: 20240071953Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above- mentioned memory device is also provided.Type: ApplicationFiled: November 6, 2023Publication date: February 29, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kai-Ming Chiang, Chao-wei Li, Wei-Lun Tsai, Chia-Min Lin, Yi-Da Tsai, Sheng-Feng Weng, Yu-Hao Chen, Sheng-Hsiang Chiu, Chih-Wei Lin, Ching-Hua Hsieh
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Publication number: 20230369480Abstract: A semiconductor device comprises an insulating region surrounding an active area having a channel direction and a transverse direction that is transverse to the channel direction. A source region and a drain region are disposed in the active area, and are spaced apart along the channel direction. A channel is disposed in the active area and is interposed between the source region and the drain region. The channel comprises a two-dimensional electron gas (2DEG). A gate line is oriented along the transverse direction and is disposed on the channel and has a gate width in the channel direction. The gate line comprises gate material. A gate line terminus is disposed at each end of the gate line. Each gate line terminus comprises the gate material. Each gate line terminus has a width in the channel direction that is at least 1.2 time the gate width.Type: ApplicationFiled: May 11, 2022Publication date: November 16, 2023Inventors: Tzu-Wen Shih, Der-Ming Kuo, Ching-Hua Chiu, Meng-Shao Hsieh, Shih-Hsiang Tai
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Publication number: 20160247973Abstract: A Light-Emitting Diode (LED) includes a light-emitting structure having a passivation layer disposed on vertical sidewalls across a first doped layer, an active layer, and a second doped layer that completely covers at least the sidewalls of the active layer. The passivation layer is formed by plasma bombardment or ion implantation of the light-emitting structure. It protects the sidewalls during subsequent processing steps and prevents current leakage around the active layer.Type: ApplicationFiled: May 5, 2016Publication date: August 25, 2016Inventors: Hung-Wen HUANG, Hsing-Kuo HSIA, Ching-Hua CHIU
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Patent number: 9324624Abstract: The present disclosure involves a method of fabricating a light-emitting diode (LED) wafer. The method first determines a target surface morphology for the LED wafer. The target surface morphology yields a maximum light output for LEDs on the LED wafer. The LED wafer is etched to form a roughened wafer surface. Thereafter, using a laser scanning microscope, the method investigates an actual surface morphology of the LED wafer. Afterwards, if the actual surface morphology differs from the target surface morphology beyond an acceptable limit, the method repeats the etching step one or more times. The etching is repeated by adjusting one or more etching parameters.Type: GrantFiled: March 27, 2012Date of Patent: April 26, 2016Assignee: EPISTAR CORPORATIONInventors: Chyi-Shyuan Chern, Hsin-Hsien Wu, Yung-Hsin Yang, Ching-Hua Chiu
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Publication number: 20160035933Abstract: A LED die and method for bonding, dicing, and forming the LED die are disclosed. In an example, the method includes forming a LED wafer, wherein the LED wafer includes a substrate and a plurality of epitaxial layers disposed over the substrate, wherein the plurality of epitaxial layers are configured to form a LED; bonding the LED wafer to a base-board to form a LED pair; and after bonding, dicing the LED pair, wherein the dicing includes simultaneously dicing the LED wafer and the base-board, thereby forming LED dies.Type: ApplicationFiled: October 14, 2015Publication date: February 4, 2016Inventors: Yea-Chen LEE, Jung-Tang CHU, Ching-Hua CHIU, Hung-Wen HUANG
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Patent number: 9117968Abstract: A light-emitting diode structure includes an AuSn or AuIn-containing bonding layer over a substrate, a metal layer disposed over the bonding layer, a p-type doped gallium nitride (p-GaN) layer disposed over the metal layer, a n-type doped gallium nitride (n-GaN) layer approximate the p-GaN layer, a multiple quantum well structure disposed between the n-GaN and p-GaN layers, and a conductive contact disposed on the n-GaN layer. The n-GaN layer includes a rough surface with randomly distributed dips. The nano-sized dips have diameters distributed between about 100 nm and about 600 nm, have a dip density ranging from about 107 grains/cm2 to about 109 grains/cm2, and are spaced from each other with an average spacing S, average diameter D, and a ratio S/D that ranges between about 1.1 and about 1.5. The conductive contact is disposed on some of the nano-sized dips of the rough surface.Type: GrantFiled: March 15, 2013Date of Patent: August 25, 2015Assignee: TSMC SOLID STATE LIGHTING LTD.Inventors: Hsing-Kuo Hsia, Ching-Hua Chiu
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Patent number: 9099632Abstract: A package structure includes: a substrate having a first side and a second side opposite to the first side; a metal layer disposed over at least a portion of the second side of the substrate; a light-reflective layer disposed over the first side of the substrate; and a photonic device bonded to the light-reflective layer from the first side. A segment of the metal layer extends through the substrate from the first side to the second side, and a portion of the substrate is completely enclosed in a cross-sectional view by the metal layer. The package structure is free of a bonding wire over the second side of the substrate.Type: GrantFiled: May 21, 2012Date of Patent: August 4, 2015Assignee: TSMC Solid State Lighting Ltd.Inventors: Chyi Shyuan Chern, Wen-Chien Fu, Hsing-Kuo Hsia, Chih-Kuang Yu, Ching-Hua Chiu, Hung-Yi Kuo
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Publication number: 20150194567Abstract: The present disclosure provides one embodiment of a method for fabricating light-emitting diode (LED) devices. The method includes forming a nano-mask layer on a first substrate, wherein the nano-mask layer has a randomly arranged grain pattern; growing a first epitaxy semiconductor layer in the first substrate, forming a nano-composite layer; growing a number of epitaxy semiconductor layers over the nano-composite layer; bonding a second substrate to the epitaxy semiconductor layers from a first side of the epitaxy semiconductor layers; applying a radiation energy to the nano-composite layer; and separating the first substrate from the epitaxy semiconductor layers from a second side of the epitaxy semiconductor layers.Type: ApplicationFiled: March 15, 2013Publication date: July 9, 2015Inventors: Hsing-Kuo Hsia, Ching-Hua Chiu
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Patent number: 9065015Abstract: A device includes a substrate; a group III-V semiconductor layer disposed over the substrate; and a seed layer disposed over the group III-V semiconductor layer. The substrate is a printed circuit board. The group III-V semiconductor layer includes a multiple quantum well (MQW) layer, a p-type doped layer, and an n-type doped layer. The seed layer includes a plurality of miniature elements. The miniature elements each contain a single-crystal material suitable for epitaxially growing the group III-V semiconductor layer. The miniature elements collectively cover less than 100% of a surface of the group III-V semiconductor layer.Type: GrantFiled: September 27, 2013Date of Patent: June 23, 2015Assignee: TSMC SOLID STATE LIGHTING LTD.Inventors: Jung-Tang Chu, Ching-Hua Chiu, Hung-Wen Huang, Yea-Chen Lee, Hsing-Kuo Hsia
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Publication number: 20150108424Abstract: A Light-Emitting Diode (LED) is formed on a sapphire substrate that is removed from the LED by grinding and then etching the sapphire substrate. The sapphire substrate is ground first to a first specified thickness using a single abrasive or multiple abrasives. The remaining sapphire substrate is removed by dry etching or wet etching.Type: ApplicationFiled: October 18, 2013Publication date: April 23, 2015Applicant: TSMC Solid State Lighting Ltd.Inventors: Hung-Wen Huang, Hsing-Kuo Hsia, Ching-Hua Chiu
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Publication number: 20140084238Abstract: A nano-patterned substrate includes a substrate and a plurality of nano-structures. The substrate has an upper surface and each of the plurality of nano-structures comprises a semiconductor buffer region and a buffer region formed on the upper surface of the substrate, wherein one of the pluralities of nano-structures has a ratio of height to diameter greater than 1, and an arc-shaped top surface.Type: ApplicationFiled: December 1, 2013Publication date: March 27, 2014Applicants: SINO-AMERICAN SILICON PRODUCTS. LNC., EPISTAR CORPORATIONInventors: Zhen-Yu Li, Ching-Hua Chiu, Hao-Chung Kuo, Tien-Chang Lu
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Publication number: 20140021483Abstract: A seed layer for growing a group 111-V semiconductor structure 1s embedded in a dielectric material on a carrier substrate. After the group 111-V semiconductor structure is grown, the dielectric material is removed by wet etch to detach the carrier substrate. The group 111-V semiconductor structure includes a thick gallium nitride layer of at least 100 microns or a light-emitting structure.Type: ApplicationFiled: September 27, 2013Publication date: January 23, 2014Applicant: TSMC Solid State Lighting Ltd.Inventors: Jung-Tang Chu, Ching-Hua Chiu, Hung-Wen Huang, Yea-Chen Lee, Hsing-Kuo Hsia
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Patent number: 8618564Abstract: The present disclosure relates to high efficiency light emitting diode devices and methods for fabricating the same. In accordance with one or more embodiments, a light emitting diode device includes a substrate having one or more recessed features formed on a surface thereof and one or more omni-directional reflectors formed to overlie the one or more recessed features. A light emitting diode layer is formed on the surface of the substrate to overlie the omni-directional reflector. The one or more omni-directional reflectors are adapted to efficiently reflect light.Type: GrantFiled: October 5, 2010Date of Patent: December 31, 2013Assignee: TSMC Solid State Lighting Ltd.Inventors: Jung-Tang Chu, Hsing-Kuo Hsia, Ching-Hua Chiu
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Patent number: 8592242Abstract: The present disclosure relates to methods for fabricating LEDs by patterning and etching an n-doped epitaxial layer to form regions of roughened surface of the n-doped layer and mesa structures adjacent to the roughened surface regions before depositing an active layer and the rest of the epitaxial layers on the mesa structures. The method includes growing epitaxial layers of an LED including an un-doped layer and an n-doped layer on a wafer of growth substrate. The method also includes patterning the n-doped layer to form a first region of the n-doped layer and a mesa region of the n-doped layer adjacent to the first region. The method further includes etching the first region of the n-doped layer to create a roughened surface. The method further includes growing additional epitaxial layers of the LED including an active layer and a p-doped layer on the mesa region of the n-doped layer.Type: GrantFiled: November 18, 2010Date of Patent: November 26, 2013Assignee: TSMC Solid State Lighting Ltd.Inventors: Hung-Wen Huang, Hsing-Kuo Hsia, Ching-Hua Chiu
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Patent number: 8563334Abstract: A Light-Emitting Diode (LED) is formed on a sapphire substrate that is removed from the LED by grinding and then etching the sapphire substrate. The sapphire substrate is ground first to a first specified thickness using a single abrasive or multiple abrasives. The remaining sapphire substrate is removed by dry etching or wet etching.Type: GrantFiled: September 14, 2010Date of Patent: October 22, 2013Assignee: TSMC Solid State Lighting Ltd.Inventors: Hung-Wen Huang, Hsing-Kuo Hsia, Ching-Hua Chiu