Abstract: A pixel array includes a plurality of scan lines, a plurality of data lines, a first active device, a second active device, a first pixel electrode and a second pixel electrode. The first active device and the second active device are electrically connected to the corresponding scan line and data line respectively. The first pixel electrode is electrically connected to the first active device through a contact hole. The second pixel electrode is electrically connected to the second active device through the contact hole.

Abstract: A signal generating circuit comprises a signal synchronizing module and a control circuit. The signal synchronizing module includes: a first delay path for delaying a target signal to generate a first delayed target signal by utilizing a first delay amount; a second delay path for delaying the target signal to generate a second delayed target signal by utilizing a second delay amount larger than the first delay amount; and a logic module, for gating the target signal to generate a first output signal according to the first delayed target signal, or gating the target signal to generate a second output signal according to the second delayed target signal. The control circuit controls the signal synchronizing module to output one of the first output signal and the second output signal according to phase difference between the target signal and a reference signal.

Abstract: A sampling circuit and a sampling method are provided, where the sampling circuit includes a first delay chain, a second delay chain, and a half-speed binary-phase detector. The first delay chain is used to delay an input signal according to an up signal and a down signal, so as to generate a first delay signal; and the second delay chain is used to delay the first delay signal according to a preset delay value, so as to generate a second delay signal. The half-speed binary-phase detector is used to sample a data signal according to edge trigger of the first delay signal and that of the second delay signal, and generate an output signal, an up signal, and a down signal according to a sampling result of the data signal.

Abstract: A signal generating circuit comprises a signal synchronizing module and a control circuit. The signal synchronizing module includes: a first delay path for delaying a target signal to generate a first delayed target signal by utilizing a first delay amount; a second delay path for delaying the target signal to generate a second delayed target signal by utilizing a second delay amount larger than the first delay amount; and a logic module, for gating the target signal to generate a first output signal according to the first delayed target signal, or gating the target signal to generate a second output signal according to the second delayed target signal. The control circuit controls the signal synchronizing module to output one of the first output signal and the second output signal according to phase difference between the target signal and a reference signal.

Abstract: A three-dimension (3D) image format converter and a 3D image format conversion method thereof are provided. The 3D image format converter includes an input circuit, a processing circuit and an output circuit. The input circuit receives a frame packing signal carrying an image signal, a first vertical synchronization signal and a first data, enable signal. The processing circuit determines an active space of the image signal according to the frame packing signal, processes the first vertical synchronization to generate a second vertical synchronization signal, and processes the first data enable signal to generate a second data enable signal. The processing circuit generates a frame sequential signal carrying the image signal, the second vertical synchronization signal and the second data enable signal. The output circuit outputs the frame sequential signal.

Abstract: A sampling circuit and a sampling method are provided, where the sampling circuit includes a first delay chain, a second delay chain, and a half-speed binary-phase detector. The first delay chain is used to delay an input signal according to an up signal and a down signal, so as to generate a first delay signal; and the second delay chain is used to delay the first delay signal according to a preset delay value, so as to generate a second delay signal. The half-speed binary-phase detector is used to sample a data signal according to edge trigger of the first delay signal and that of the second delay signal, and generate an output signal, an up signal, and a down signal according to a sampling result of the data signal.

Abstract: An exemplary Mobile High-Definition Link (MHL) data converter includes: a data decoding circuit, arranged for decoding an input data according to an MHL specification, and outputting a decoded data; and a data parsing circuit, coupled to the data decoding circuit, arranged for parsing out a plurality of output data from the decoded data. An MHL data converting method includes: decoding an input data according to an MHL specification, and outputting a decoded data; and parsing out a plurality of output data from the decoded data.

Abstract: A pixel structure includes a substrate, a gate line and a gate electrode disposed on the substrate, an insulating layer covering the substrate, a semiconductor layer disposed on the insulating layer, a data line, a source electrode, and a drain electrode which are disposed on the insulating layer and the semiconductor layer, a planarization layer disposed on the data line, the source electrode, and the drain electrode, and a pixel electrode disposed on the planarization layer. The planarization layer has a through hole exposing the drain electrode. The pixel electrode is electrically connected to the drain electrode via the through hole and includes an opaque main electrode and a plurality of transparent branch electrodes disposed on the planarization layer. One end of each transparent branch electrode is electrically connected to the opaque main electrode.

Abstract: A liquid crystal display panel includes a substrate, gate lines, data lines, pixel electrodes, an insulating layer, patterned common electrodes and connection lines. Each pixel electrode includes a transparent electrode. The insulating layer covers the pixel electrodes. The patterned common electrodes are disposed on the insulating layer. Each patterned common electrodes includes a plurality of electrode branches, and at least one slit disposed between two adjacent electrode branches. The patterned common electrode includes a transparent electrode. The connection line is disposed on the insulating layer, and each connection line is in contact with and electrically connects to the patterned common electrodes of two adjacent sub-pixel regions.

Abstract: An MVA LCD device includes a first alignment region, a second alignment region, a third alignment region, and a fourth alignment region. The liquid crystal molecules disposed in the first alignment region have a first aligning direction, and the azimuth angle of the first aligning direction is substantially between 70 and 110 degrees. The liquid crystal molecules disposed in the second alignment region have a second aligning direction, and the azimuth angle of the second aligning direction is substantially between 160 and 200 degrees. The liquid crystal molecules disposed in the third alignment region have a third aligning direction, and the azimuth angle of the third aligning direction is substantially between 250 and 290 degrees. The liquid crystal molecules disposed in the fourth alignment region have a fourth aligning direction, and the azimuth angle of the fourth aligning direction is substantially between ?20 and 20 degrees.

Abstract: A flat display device integrated with a photovoltaic cell is disclosed. The flat display device includes a first substrate, a second substrate, a display medium layer, a first photovoltaic cell, a connecting layer and a conductive structure. The display medium layer is sealed between the first and second substrates. The first photovoltaic cell is disposed on the first substrate. The connecting layer is disposed on the second substrate and is capable of electrically connecting the first photovoltaic cell to an external circuit. The conductive structure is disposed between the first and second substrates, and is electrically connected with the first photovoltaic cell and the connecting layer.

Abstract: A measuring apparatus for measuring a stereo video format includes an active space measuring circuit and a decision circuit. The active space measuring circuit is utilized for determining a position of an active space of a frame packing to generate an active space measuring result according to pixels values of a plurality of scan lines of the frame packing. The decision circuit is coupled to the active space measuring circuit, and is utilized for determining the stereo video format according to at least the active space measuring result.

Abstract: An image control device is disclosed, which may be cooperated with a display device. The display device may cooperates with a pair of glasses and present a first image frame, a second image frame, a third image frame, and a fourth image frame sequentially. A first lens of the glasses is non-opaque when the display device presents the first and the third image frames. A second lens of the glasses is non-opaque when the display device presents the second and the fourth image frames. The image control device comprises an input end for receiving light-sensing signals from one or more sensors, and a signal processing device for configuring the transparency of the lenses and/or for configuring the duration in which the first lens and/or the second lens is non-opaque according to the light sensing signals.

Abstract: A display panel having a reflective region and a transparent region is provided. The reflective region and the transparent region respectively have sub-pixel regions. The display panel includes a first substrate, a second substrate, a plurality of color filter patterns, a single complementary color filter pattern and a display medium. The first substrate has a plurality of pixel structures disposed corresponding to the sub-pixel regions. The second substrate is disposed opposite to the first substrate. The color filter patterns are respectively disposed in the sub-pixel regions of the transparent region on the first or second substrate. The single complementary color filter pattern is disposed in the sub-pixel regions of the reflective region on the first or second substrate. The sub-pixel regions of the reflective region are not completely covered by the single complementary color filter pattern. The display medium is disposed between the first substrate and second substrate.

Abstract: A transflective LCD device includes an array substrate and a color filter. The substrate includes a plurality gate lines, a plurality of common lines, and a plurality of data lines substantially crossing the gate lines to define a plurality of sub-pixel regions. Each sub-pixel region has a reflective area and a transmissive area. Two of the reflective area of two adjacent sub-pixel regions in the same column are juxtaposed to each other. The color filter has a plurality of sub-pixel regions respectively aligned with the sub-pixel regions of the array substrate. The color filter includes an insulating layer disposed on the reflective area of a respective sub-pixel region. An LC layer is disposed between the array substrate and the color filter.

Abstract: A touch sensing substrate includes a substrate, first and second sensing series, a first dielectric layer, first and second dummy sensing series, a second dielectric layer, and a common electrode. The first sensing series are electrically insulated from each other, and so are the second sensing series. The first and the second sensing series are covered by the first dielectric layer. The first and the second dummy sensing series are disposed on the first dielectric layer. The first and the second dummy sensing series are disposed above the first and the second sensing series, respectively, and the dummy sensing series and the sensing series corresponding thereto have the same potential. The first and the second dummy sensing series are covered by the second dielectric layer. The common electrode is disposed on the second dielectric layer. A touch sensing liquid crystal display having the above-mentioned touch sensing substrate is also provided.

Abstract: A flat display device integrated with a photovoltaic cell is disclosed. The flat display device includes a first substrate, a second substrate, a display medium layer, a first photovoltaic cell, a connecting layer and a conductive structure. The display medium layer is sealed between the first and second substrates. The first photovoltaic cell is disposed on the first substrate. The connecting layer is disposed on the second substrate and is capable of electrically connecting the first photovoltaic cell to an external circuit. The conductive structure is disposed between the first and second substrates, and is electrically connected with the first photovoltaic cell and the connecting layer.

Abstract: A pixel structure is disclosed. The pixel structure is suitable to be disposed on a substrate and includes a first pixel electrode, a second pixel electrode and a top gate TFT. The first pixel electrode and the second pixel electrode are disposed over the substrate, wherein the first pixel electrode and the second pixel electrode are separated from each other. The top gate TFT is disposed between the substrate and the first pixel electrode and includes a patterned semiconductor layer and a gate.

Abstract: A pixel structure includes a substrate, a gate line and a gate electrode disposed on the substrate, an insulating layer covering the substrate, a semiconductor layer disposed on the insulating layer, a data line, a source electrode, and a drain electrode which are disposed on the insulating layer and the semiconductor layer, a planarization layer disposed on the data line, the source electrode, and the drain electrode, and a pixel electrode disposed on the planarization layer. The planarization layer has a through hole exposing the drain electrode. The pixel electrode is electrically connected to the drain electrode via the through hole and includes an opaque main electrode and a plurality of transparent branch electrodes disposed on the planarization layer. One end of each transparent branch electrode is electrically connected to the opaque main electrode.

Abstract: A transreflective LCD has a TFT array plate, a color filter plate and a liquid crystal therebetween. A trench is in the overcoat layer of the TFT array plate and/or the color filter plate. The trench can be located in a transmission area or in a reflective area of a pixel. A conformal transparent electrode is located therein, and an overcoat material is filled up in the trench.