Patents by Inventor Chiyu Zhu

Chiyu Zhu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • METHOD FOR FORMING A SEMICONDUCTOR DEVICE STRUCTURE AND RELATED SEMICONDUCTOR DEVICE STRUCTURES
    Publication number: 20200227325
    Abstract: A method for forming a semiconductor device structure is disclosure. The method may include, depositing an NMOS gate dielectric and a PMOS gate dielectric over a semiconductor substrate, depositing a first work function metal over the NMOS gate dielectric and over the PMOS gate dielectric, removing the first work function metal over the PMOS gate dielectric, and depositing a second work function metal over the NMOS gate dielectric and over the PMOS gate dielectric. Semiconductor device structures including desired metal gate electrodes deposited by the methods of the disclosure are also disclosed.
    Type: Application
    Filed: March 30, 2020
    Publication date: July 16, 2020
    Inventors: Qi Xie, Chiyu Zhu, Kiran Shrestha, Pauline Calka, Oreste Madia, Jan Willem Maes, Michael Eugene Givens
  • Thermal atomic layer etching processes
    Patent number: 10662533
    Abstract: Thermal atomic layer etching processes are disclosed. In some embodiments, the methods comprise at least one etch cycle in which the substrate is alternately and sequentially exposed to a first vapor phase halide reactant and a second vapor halide reactant. In some embodiments, the first reactant may comprise an organic halide compound. During the thermal ALE cycle, the substrate is not contacted with a plasma reactant.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: May 26, 2020
    Assignee: ASM IP Holding B.V.
    Inventors: Tom E. Blomberg, Varun Sharma, Suvi P. Haukka, Marko J. Tuominen, Chiyu Zhu
  • Atomic layer etching processes
    Patent number: 10665425
    Abstract: Atomic layer etching (ALE) processes are disclosed. In some embodiments, the methods comprise at least one etch cycle in which the substrate is alternately and sequentially exposed to a first vapor phase non-metal halide reactant and a second vapor phase halide reactant. In some embodiments both the first and second reactants are chloride reactants. In some embodiments the first reactant is fluorinating gas and the second reactant is a chlorinating gas. In some embodiments a thermal ALE cycle is used in which the substrate is not contacted with a plasma reactant.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: May 26, 2020
    Assignee: ASM IP Holding B.V.
    Inventors: Tom E. Blomberg, Varun Sharma, Suvi P. Haukka, Marko J. Tuominen, Chiyu Zhu
  • Thermal atomic layer etching processes
    Patent number: 10662534
    Abstract: Thermal atomic layer etching processes are disclosed. In some embodiments, the methods comprise at least one etch cycle in which the substrate is alternately and sequentially exposed to a first vapor phase halide reactant and a second vapor halide reactant. In some embodiments, the first reactant may comprise an organic halide compound. During the thermal ALE cycle, the substrate is not contacted with a plasma reactant.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: May 26, 2020
    Assignee: ASM IP Holding B.V.
    Inventors: Tom E. Blomberg, Varun Sharma, Suvi Haukka, Marko Tuominen, Chiyu Zhu
  • Titanium aluminum and tantalum aluminum thin films
    Patent number: 10636889
    Abstract: A process for depositing titanium aluminum or tantalum aluminum thin films comprising nitrogen on a substrate in a reaction space can include at least one deposition cycle. The deposition cycle can include alternately and sequentially contacting the substrate with a vapor phase Ti or Ta precursor and a vapor phase Al precursor. At least one of the vapor phase Ti or Ta precursor and the vapor phase Al precursor may contact the substrate in the presence of a vapor phase nitrogen precursor.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: April 28, 2020
    Assignee: ASM IP Holding B.V.
    Inventors: Suvi Haukka, Michael Givens, Eric Shero, Jerry Winkler, Petri Räisänen, Timo Asikainen, Chiyu Zhu, Jaakko Anttila
  • METHOD FOR FORMING DOPED METAL OXIDE FILMS ON A SUBSTRATE BY CYCLICAL DEPOSITION AND RELATED SEMICONDUCTOR DEVICE STRUCTURES
    Publication number: 20200118817
    Abstract: Methods for forming a doped metal oxide film on a substrate by cyclical deposition are provided. In some embodiments, methods may include contacting the substrate with a first reactant comprising a metal halide source, contacting the substrate with a second reactant comprising a hydrogenated source and contacting the substrate with a third reactant comprising an oxide source. In some embodiments, related semiconductor device structures may include a doped metal oxide film formed by cyclical deposition processes.
    Type: Application
    Filed: December 13, 2019
    Publication date: April 16, 2020
    Inventors: Tom Blomberg, Chiyu Zhu
  • SELECTIVE DEPOSITION METHOD TO FORM AIR GAPS
    Publication number: 20200105579
    Abstract: A method for depositing a film to form an air gap within a semiconductor device is disclosed. An exemplary method comprises pulsing a metal halide precursor onto the substrate and pulsing an oxygen precursor onto a selective deposition surface. The method can be used to form an air gap to, for example, reduce a parasitic resistance of the semiconductor device.
    Type: Application
    Filed: November 15, 2019
    Publication date: April 2, 2020
    Inventor: Chiyu Zhu
  • Method for forming a semiconductor device structure comprising a gate fill metal
    Patent number: 10607895
    Abstract: A method for forming a semiconductor device structure is disclosure. The method may include, depositing an NMOS gate dielectric and a PMOS gate dielectric over a semiconductor substrate, depositing a first work function metal over the NMOS gate dielectric and over the PMOS gate dielectric, removing the first work function metal over the PMOS gate dielectric, and depositing a second work function metal over the NMOS gate dielectric and over the PMOS gate dielectric. Semiconductor device structures including desired metal gate electrodes deposited by the methods of the disclosure are also disclosed.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: March 31, 2020
    Assignee: ASM IP Holdings B.V.
    Inventors: Qi Xie, Chiyu Zhu, Kiran Shrestha, Pauline Calka, Oreste Madia, Jan Willem Maes, Michael Eugene Givens
  • Selective deposition of aluminum and nitrogen containing material
    Patent number: 10566185
    Abstract: Methods are provided for selectively depositing Al and N containing material on a first conductive surface of a substrate relative to a second, dielectric surface of the same substrate. In some aspects, methods of forming an Al and N containing protective layer or etch stop layer for use in integrated circuit fabrication are provided.
    Type: Grant
    Filed: August 5, 2015
    Date of Patent: February 18, 2020
    Assignee: ASM IP Holding B.V.
    Inventors: Han Wang, Qi Xie, Delphine Longrie, Jan Willem Maes, David de Roest, Julian Hsieh, Chiyu Zhu, Timo Asikainen
  • Selective deposition of aluminum and nitrogen containing material
    Patent number: 10553482
    Abstract: Methods are provided for selectively depositing Al and N containing material on a first conductive surface of a substrate relative to a second, dielectric surface of the same substrate. In some aspects, methods of forming an Al and N containing protective layer or etch stop layer for use in integrated circuit fabrication are provided.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: February 4, 2020
    Assignee: ASM IP Holding B.V.
    Inventors: Han Wang, Qi Xie, Delphine Longrie, Jan Willem Maes, David de Roest, Julian Hsieh, Chiyu Zhu, Timo Asikainen, Krzysztof Kachel, Harald Profijt
  • Selective deposition method to form air gaps
    Patent number: 10541173
    Abstract: A method for depositing a film to form an air gap within a semiconductor device is disclosed. An exemplary method comprises pulsing a metal halide precursor onto the substrate and pulsing an oxygen precursor onto a selective deposition surface. The method can be used to form an air gap to, for example, reduce a parasitic resistance of the semiconductor device.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: January 21, 2020
    Assignee: ASM IP Holding B.V.
    Inventor: Chiyu Zhu
  • Method for forming doped metal oxide films on a substrate by cyclical deposition and related semiconductor device structures
    Patent number: 10529563
    Abstract: Methods for forming a doped metal oxide film on a substrate by cyclical deposition are provided. In some embodiments, methods may include contacting the substrate with a first reactant comprising a metal halide source, contacting the substrate with a second reactant comprising a hydrogenated source and contacting the substrate with a third reactant comprising an oxide source. In some embodiments, related semiconductor device structures may include a doped metal oxide film formed by cyclical deposition processes.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: January 7, 2020
    Assignee: ASM IP Holdings B.V.
    Inventors: Tom Blomberg, Chiyu Zhu
  • REACTOR, SYSTEM INCLUDING THE REACTOR, AND METHODS OF MANUFACTURING AND USING SAME
    Publication number: 20190287769
    Abstract: A reactor for processing substrates and methods for manufacturing and using the reactor are disclosed. Specifically, the reactor can include a material that forms gas compounds. The gas compounds are then easily removed from the reactor, thus reducing or avoiding contamination of the substrates in the reactor that would otherwise arise.
    Type: Application
    Filed: March 16, 2018
    Publication date: September 19, 2019
    Inventors: Tom Blomberg, Varun Sharma, Chiyu Zhu
  • THERMAL ATOMIC LAYER ETCHING PROCESSES
    Publication number: 20190249312
    Abstract: Thermal atomic layer etching processes are disclosed. In some embodiments, the methods comprise at least one etch cycle in which the substrate is alternately and sequentially exposed to a first vapor phase halide reactant and a second vapor halide reactant. In some embodiments, the first reactant may comprise an organic halide compound. During the thermal ALE cycle, the substrate is not contacted with a plasma reactant.
    Type: Application
    Filed: April 22, 2019
    Publication date: August 15, 2019
    Inventors: Tom E. Blomberg, Varun Sharma, Suvi P. Haukka, Marko J. Tuominen, Chiyu Zhu
  • THERMAL ATOMIC LAYER ETCHING PROCESSES
    Publication number: 20190242019
    Abstract: Thermal atomic layer etching processes are disclosed. In some embodiments, the methods comprise at least one etch cycle in which the substrate is alternately and sequentially exposed to a first vapor phase halide reactant and a second vapor halide reactant. In some embodiments, the first reactant may comprise an organic halide compound. During the thermal ALE cycle, the substrate is not contacted with a plasma reactant.
    Type: Application
    Filed: April 22, 2019
    Publication date: August 8, 2019
    Inventors: Tom E. Blomberg, Varun Sharma, Suvi Haukka, Marko Tuominen, Chiyu Zhu
  • ATOMIC LAYER ETCHING PROCESSES
    Publication number: 20190244786
    Abstract: Atomic layer etching (ALE) processes are disclosed. In some embodiments, the methods comprise at least one etch cycle in which the substrate is alternately and sequentially exposed to a first vapor phase non-metal halide reactant and a second vapor phase halide reactant. In some embodiments both the first and second reactants are chloride reactants. In some embodiments the first reactant is fluorinating gas and the second reactant is a chlorinating gas. In some embodiments a thermal ALE cycle is used in which the substrate is not contacted with a plasma reactant.
    Type: Application
    Filed: April 22, 2019
    Publication date: August 8, 2019
    Inventors: Tom E. Blomberg, Varun Sharma, Suvi P. Haukka, Marko J. Tuominen, Chiyu Zhu
  • DEPOSITION OF METAL BORIDES
    Publication number: 20190153593
    Abstract: A method for depositing a metal film onto a substrate is disclosed. In particular, the method comprises pulsing a metal halide precursor onto the substrate and pulsing a decaborane precursor onto the substrate. A reaction between the metal halide precursor and the decaborane precursor forms a metal film, specifically a metal boride.
    Type: Application
    Filed: January 25, 2019
    Publication date: May 23, 2019
    Inventors: Chiyu Zhu, Kiran Shrestha, Suvi Haukka
  • NbMC LAYERS
    Publication number: 20190140067
    Abstract: Methods of forming thin-film structures including one or more NbMC layers, and structures and devices including the one or more NbMC layers are disclosed. The NbMC layers enable tuning of various structure and device properties, including resistivity, current leakage, and work function.
    Type: Application
    Filed: January 4, 2019
    Publication date: May 9, 2019
    Applicant: ASM IP Holding B.V.
    Inventors: Chiyu Zhu, Timo Asikainen, Robert Brennan Milligan
  • Thermal atomic layer etching processes
    Patent number: 10280519
    Abstract: Thermal atomic layer etching processes are disclosed. In some embodiments, the methods comprise at least one etch cycle in which the substrate is alternately and sequentially exposed to a first vapor phase halide reactant and a second vapor halide reactant. In some embodiments, the first reactant may comprise an organic halide compound. During the thermal ALE cycle, the substrate is not contacted with a plasma reactant.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: May 7, 2019
    Assignee: ASM IP HOLDING B.V.
    Inventors: Tom E. Blomberg, Varun Sharma, Suvi Haukka, Marko Tuominen, Chiyu Zhu
  • Atomic layer etching processes
    Patent number: 10283319
    Abstract: Atomic layer etching (ALE) processes are disclosed. In some embodiments, the methods comprise at least one etch cycle in which the substrate is alternately and sequentially exposed to a first vapor phase non-metal halide reactant and a second vapor phase halide reactant. In some embodiments both the first and second reactants are chloride reactants. In some embodiments the first reactant is fluorinating gas and the second reactant is a chlorinating gas. In some embodiments a thermal ALE cycle is used in which the substrate is not contacted with a plasma reactant.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: May 7, 2019
    Assignee: ASM IP HOLDING B.V.
    Inventors: Tom E. Blomberg, Varun Sharma, Suvi Haukka, Marko Tuominen, Chiyu Zhu