Abstract: Systems, devices, and methods transcribe words recorded in audio data. A computer-generated transcript is provided. The transcript comprises records for each word in the computer-generated transcript. At least one confirmation input is received for each record. The at least one confirmation input modifies a selected record and automatically identifies a next record for receiving a next confirmation input. A sequence of confirmation inputs may rapidly modify and validate each record in a sequence of records in the computer-generated transcript. A validated transcript is generated from the modified records and is provided from an evidence management system.

Abstract: Systems, devices, and methods transcribe words recorded in audio data. A computer-generated transcript is provided. The transcript comprises records for each word in the computer-generated transcript. At least one confirmation input is received for each record. The at least one confirmation input modifies a selected record and automatically identifies a next record for receiving a next confirmation input. A sequence of confirmation inputs may rapidly modify and validate each record in a sequence of records in the computer-generated transcript. A validated transcript is generated from the modified records and is provided from an evidence management system.

Abstract: Examples of systems and methods for audio transcription are described. Audio data may be obtained from multiple recording devices at or near a scene. Audio data from multiple recording devices may be used to generate a final transcription. For example, when transcribing audio data from one recording device, audio data from another recording device may be used to generate the final transcript. The data from the second recording device may be used when it is determined that the recording devices were in proximity at the time the relevant portions of audio data were recorded and/or when a portion of the audio from the second recording device is verified to correspond with a portion of the audio from the first recording device. In some examples, data from the second recording device may be used when data from the first recording device is determined to be of low quality.

Abstract: Systems, devices, and methods transcribe words recorded in audio data. A computer-generated transcript is provided. The transcript comprises records for each word in the computer-generated transcript. At least one confirmation input is received for each record. The at least one confirmation input modifies a selected record and automatically identifies a next record for receiving a next confirmation input. A sequence of confirmation inputs may rapidly modify and validate each record in a sequence of records in the computer-generated transcript. A validated transcript is generated from the modified records and is provided from an evidence management system.

Abstract: A radio frequency identification (RFID) device and method of fabrication are presented. The RFID device includes an RFID antenna, a capacitor, and an RFID integrated circuit. The RFID antenna includes an elongate conductive trace disposed within an antenna area of the RFID device, and the capacitor includes an elongate capacitive structure for storing power. The elongate capacitive structure is aligned with the elongate conductive trace and embedded within the antenna area of the RFID device. The RFID integrated circuit is electrically coupled to the RFID antenna and to the capacitor, and the capacitor stores power within the antenna area of the RFID device to facilitate RFID integrated circuit functionality.

Abstract: Sub-100 nanometer semiconductor devices and methods and program products for manufacturing devices are provided, in particular inductors comprising a plurality of spaced parallel metal lines disposed on a dielectric surface and each having width, heights, spacing and cross-sectional areas determined as a function of Design Rule Check rules. For one planarization process rule a metal density ratio of 80% metal to 20% dielectric surface is determined and produced. In one example a sum of metal line spacing gaps is less than a sum of metal line interior sidewall heights. In one aspect at least one of line height, width and line spacing dimensions is selected to optimize one or more chip yield, chip performance, chip manufacturability and inductor Q factor parameters.

Abstract: A method and system to predict lithography focus error using chip topography data is disclosed. The chip topography data may be measured or simulated topography data. A plane is best fitted to the topography data, and residuals are computed. The residuals are then used to make a prediction regarding the focus error. The density ratio of metal to dielectric may also be used as a factor in determining the predicted focus error.

Abstract: An identification method and identification device are presented employing radio frequency and acoustic wave communication modes. The identification method includes: receiving at an acoustic wave and radio frequency identification device an acoustic wave signal of a first frequency and a radio frequency signal of a second frequency, where the acoustic wave signal and the radio frequency signal are received from an acoustic wave and radio frequency identification reader, and the first frequency and the second frequency are different frequencies; and responding to the receiving by transmitting at least one of an acoustic wave identification (AWID) or a radio frequency identification (RFID) from the acoustic wave and radio frequency identification device.

Abstract: A method and system to predict lithography focus error using chip topography data is disclosed. The chip topography data may be measured or simulated topography data. A plane is best fitted to the topography data, and residuals are computed. The residuals are then used to make a prediction regarding the focus error. The density ratio of metal to dielectric may also be used as a factor in determining the predicted focus error.

Abstract: A method and system to predict lithography focus error using chip topography data is disclosed. The chip topography data may be measured or simulated topography data. A plane is best fitted to the topography data, and residuals are computed. The residuals are then used to make a prediction regarding the focus error. The density ratio of metal to dielectric may also be used as a factor in determining the predicted focus error.

Abstract: A method and system to predict lithography focus error using chip topography data is disclosed. The chip topography data may be measured or simulated topography data. A plane is best fitted to the topography data, and residuals are computed. The residuals are then used to make a prediction regarding the focus error. The density ratio of metal to dielectric may also be used as a factor in determining the predicted focus error.

Abstract: Back-end-of-line (BEOL) circuit structures and methods are provided for blocking externally-originating or internally-originating electromagnetic edge interference. One such BEOL circuit structure includes a semiconductor substrate supporting one or more integrated circuits, and multiple BEOL layers disposed over the semiconductor substrate. The multiple BEOL layers extend to an edge of the circuit structure and include at least one vertically-extending conductive pattern disposed adjacent to the edge of the circuit structure. The vertically-extending conductive pattern is defined, at least partially, by a plurality of elements disposed in the multiple BEOL layers. The plurality of elements are uniformly arrayed at the edge of the circuit structure in a first direction or a second direction throughout at least a portion thereof.

Abstract: Sub-100 nanometer semiconductor devices and methods and program products for manufacturing devices are provided, in particular inductors comprising a plurality of spaced parallel metal lines disposed on a dielectric surface and each having width, heights, spacing and cross-sectional areas determined as a function of Design Rule Check rules. For one planarization process rule a metal density ratio of 80% metal to 20% dielectric surface is determined and produced. In one example a sum of metal line spacing gaps is less than a sum of metal line interior sidewall heights. In one aspect at least one of line height, width and line spacing dimensions is selected to optimize one or more chip yield, chip performance, chip manufacturability and inductor Q factor parameters.

Abstract: A method and system to predict lithography focus error using chip topography data is disclosed. The chip topography data may be measured or simulated topography data. A plane is best fitted to the topography data, and residuals are computed. The residuals are then used to make a prediction regarding the focus error. The density ratio of metal to dielectric may also be used as a factor in determining the predicted focus error.

Abstract: Sub-100 nanometer semiconductor devices and methods and program products for manufacturing devices are provided, in particular inductors comprising a plurality of spaced parallel metal lines disposed on a dielectric surface and each having width, heights, spacing and cross-sectional areas determined as a function of Design Rule Check rules. For one planarization process rule a metal density ratio of 80% metal to 20% dielectric surface is determined and produced. In one example a sum of metal line spacing gaps is less than a sum of metal line interior sidewall heights. In one aspect at least one of line height, width and line spacing dimensions is selected to optimize one or more chip yield, chip performance, chip manufacturability and inductor Q factor parameters.

Abstract: Back-end-of-line (BEOL) circuit structures and methods are provided for blocking externally-originating or internally-originating electromagnetic edge interference. One such BEOL circuit structure includes a semiconductor substrate supporting one or more integrated circuits, and multiple BEOL layers disposed over the semiconductor substrate. The multiple BEOL layers extend to an edge of the circuit structure and include at least one vertically-extending conductive pattern disposed adjacent to the edge of the circuit structure. The vertically-extending conductive pattern is defined, at least partially, by a plurality of elements disposed in the multiple BEOL layers. The plurality of elements are uniformly arrayed at the edge of the circuit structure in a first direction or a second direction throughout at least a portion thereof.

Abstract: An apparatus and method for recycling and reusing charge in an electronic circuit. The apparatus includes at least one capacitor coupled to a circuit block in the electronic circuit, the capacitor being configured to collect current charge consumed by the circuit block when set to a charge collection mode, and a voltage level comparator configured to detect a fully charged state when the capacitor is fully charged. Further, the apparatus includes a first electrical switch configured to allow, once the fully charged state is detected, the capacitor to switch to a discharge mode for discharging the current charge collected back into the power supply for reuse by the electrical system and a second switch configured to allow, after the capacitor has fully discharged the current charge collected, the capacitor to switch back to the charge collection mode, such that, the current charge is recycled and reused by the electrical system.

Abstract: Back-end-of-line (BEOL) circuit structures and methods are provided for blocking externally-originating or internally-originating electromagnetic edge interference. One such BEOL circuit structure includes a semiconductor substrate supporting one or more integrated circuits, and multiple BEOL layers disposed over the semiconductor substrate. The multiple BEOL layers extend to an edge of the circuit structure and include at least one vertically-extending conductive pattern disposed adjacent to the edge of the circuit structure. The vertically-extending conductive pattern is defined, at least partially, by a plurality of elements disposed in the multiple BEOL layers. The plurality of elements are uniformly arrayed at the edge of the circuit structure in a first direction or a second direction throughout at least a portion thereof.

Abstract: Capacitance circuits are provided disposing a lower vertical-native capacitor metal layer above a planar front-end-of-line semiconductor base substrate, planar metal bottom plates spaced a bottom plate distance from the base and top plates above the bottom plates spaced a top plate distance from the base defining metal-insulator-metal capacitors, top plate footprints disposed above the base substrate smaller than bottom plate footprints and exposing bottom plate remainder upper lateral connector surfaces; disposing parallel positive port and negative port upper vertical-native capacitor metal layers over and each connected to top plate and bottom plate upper remainder lateral connector surface. Moreover, electrical connecting of the first top plate and the second bottom plate to the positive port metal layer and of the second top plate and the first bottom to the negative port metal layer impart equal total negative port and positive port metal-insulator-metal capacitor extrinsic capacitance.

Abstract: In a random number generator, a first converter converts a first analog noise signal into a random digital clock signal and a second converter samples a second analog noise signal asynchronous to the first analog noise signal in response to the random digital clock signal and generates a random digital number stream. In one aspect, a random number generator output block samples the second converter random digital number stream in response to the random digital clock signal and generates a random number generator block output. In another aspect a pseudo noise source state machine generates the random digital clock signal in response to a first seed generated from the first analog noise signal, a second seed from process variation digital amplifier, and a past machine state.