Patents by Inventor Choongyeun Cho
Choongyeun Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7902880Abstract: Circuits and methods are provided for facilitating transitioning of a digital circuit from backgate biased standby mode to active mode. The digital circuit includes a semiconductor substrate, multiple n-channel transistors disposed at least partially in one or more p-type wells in the semiconductor substrate, multiple p-channel transistors disposed at least partially in one or more n-type wells in the semiconductor substrate, and a backgate control circuit. The backgate control circuit is electrically coupled to the p-type well(s) and to the n-type well(s) to facilitate transitioning of the multiple n-channel transistors and the multiple p-channel transistors from backgate biased standby mode to active mode by automatically shunting charge from the n-type well(s) to the p-type well(s) until a well voltage threshold is reached indicative of a completed transition of the transistors from backgate biased standby mode to active mode.Type: GrantFiled: July 27, 2010Date of Patent: March 8, 2011Assignee: International Business Machines CorporationInventors: Choongyeun Cho, Daeik Kim, Jonghae Kim, Moon Ju Kim
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Publication number: 20100295156Abstract: Capacitance circuits are provided disposing a lower vertical-native capacitor metal layer above a planar front-end-of-line semiconductor base substrate, planar metal bottom plates spaced a bottom plate distance from the base and top plates above the bottom plates spaced a top plate distance from the base defining metal-insulator-metal capacitors, top plate footprints disposed above the base substrate smaller than bottom plate footprints and exposing bottom plate remainder upper lateral connector surfaces; disposing parallel positive port and negative port upper vertical-native capacitor metal layers over and each connected to top plate and bottom plate upper remainder lateral connector surface. Moreover, electrical connecting of the first top plate and the second bottom plate to the positive port metal layer and of the second top plate and the first bottom to the negative port metal layer impart equal total negative port and positive port metal-insulator-metal capacitor extrinsic capacitance.Type: ApplicationFiled: August 6, 2010Publication date: November 25, 2010Applicant: International Business Machines CorporationInventors: Choongyeun Cho, Jonghae Kim, Moon J. Kim, Jean-Olivier Plouchart, Robert E. Trzcinski
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Patent number: 7838384Abstract: Methods, articles and design structures for capacitance circuits are provided disposing a lower vertical-native capacitor metal layer above a planar front-end-of-line semiconductor base substrate, planar metal bottom plates spaced a bottom plate distance from the base and top plates above the bottom plates spaced a top plate distance from the base defining metal-insulator-metal capacitors, top plate footprints disposed above the base substrate smaller than bottom plate footprints and exposing bottom plate remainder upper lateral connector surfaces; disposing parallel positive port and negative port upper vertical-native capacitor metal layers over and each connected to top plate and bottom plate upper remainder lateral connector surface.Type: GrantFiled: January 8, 2008Date of Patent: November 23, 2010Assignee: International Business Machines CorporationInventors: Choongyeun Cho, Jonghae Kim, Moon J. Kim, Jean-Olivier Plouchart, Robert E. Trzcinski
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Publication number: 20100285616Abstract: Circuits and methods are provided for facilitating transitioning of a digital circuit from backgate biased standby mode to active mode. The digital circuit includes a semiconductor substrate, multiple n-channel transistors disposed at least partially in one or more p-type wells in the semiconductor substrate, multiple p-channel transistors disposed at least partially in one or more n-type wells in the semiconductor substrate, and a backgate control circuit. The backgate control circuit is electrically coupled to the p-type well(s) and to the n-type well(s) to facilitate transitioning of the multiple n-channel transistors and the multiple p-channel transistors from backgate biased standby mode to active mode by automatically shunting charge from the n-type well(s) to the p-type well(s) until a well voltage threshold is reached indicative of a completed transition of the transistors from backgate biased standby mode to active mode.Type: ApplicationFiled: July 27, 2010Publication date: November 11, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Choongyeun CHO, Daeik KIM, Jonghae KIM, Moon Ju KIM
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Patent number: 7821110Abstract: Back end of line (BEOL) circuit structures and methods are provided for blocking externally-originating or internally-originating electromagnetic interference. One such BEOL circuit structure includes one or more semiconductor substrates supporting one or more integrated circuits, and one or more BEOL layers disposed over the semiconductor substrate(s). At least one BEOL layer includes a conductive pattern defined at least partially by a plurality of elements arrayed in a first direction and a second direction throughout at least a portion thereof. The plurality of elements are sized and positioned in at least one of the first and second directions to block electromagnetic interference of a particular wavelength from passing therethrough. In one implementation, a first conductive pattern of a first BEOL layer polarizes electromagnetic interference, and a second conductive pattern of a second BEOL layer blocks the polarized electromagnetic interference.Type: GrantFiled: May 11, 2007Date of Patent: October 26, 2010Assignee: International Business Machines CorporationInventors: Dae Ik Kim, Jonghae Kim, Moon Ju Kim, Choongyeun Cho
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Patent number: 7804329Abstract: The present invention enables fast transition between sleep and normal modes for circuits such as digital circuits. This invention utilizes chip internal charge transfer operations to put the circuit into fast sleep. The invention reduces external power involvement, and it expedites the sleep mode transition time by limiting charge transfers within the circuit. The fast sleep and fast wake-up enable more efficient power management of the system. This functionality also maximizes performance per power, and provides a more energy efficient computing architecture.Type: GrantFiled: November 21, 2008Date of Patent: September 28, 2010Assignee: International Business Machines CorporationInventors: Choongyeun Cho, Elmer K. Corbin, Daeik Kim, Moon J. Kim
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Patent number: 7791403Abstract: Circuits and methods are provided for facilitating transitioning of a digital circuit from backgate biased standby mode to active mode. The digital circuit includes a semiconductor substrate, multiple n-channel transistors disposed at least partially in one or more p-type wells in the semiconductor substrate, multiple p-channel transistors disposed at least partially in one or more n-type wells in the semiconductor substrate, and a backgate control circuit. The backgate control circuit is electrically coupled to the p-type well(s) and to the n-type well(s) to facilitate transitioning of the multiple n-channel transistors and the multiple p-channel transistors from backgate biased standby mode to active mode by automatically shunting charge from the n-type well(s) to the p-type well(s) until a well voltage threshold is reached indicative of a completed transition of the transistors from backgate biased standby mode to active mode.Type: GrantFiled: September 8, 2008Date of Patent: September 7, 2010Assignee: International Business Machines CorporationInventors: Choongyeun Cho, Daeik Kim, Jonghae Kim, Moon Ju Kim
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Publication number: 20100127730Abstract: The present invention enables fast transition between sleep and normal modes for circuits such as digital circuits. This invention utilizes chip internal charge transfer operations to put the circuit into fast sleep. The invention reduces external power involvement, and it expedites the sleep mode transition time by limiting charge transfers within the circuit. The fast sleep and fast wake-up enable more efficient power management of the system. This functionality also maximizes performance per power, and provides a more energy efficient computing architecture.Type: ApplicationFiled: November 21, 2008Publication date: May 27, 2010Applicant: International Business Machines CorporationInventors: Choongyeun Cho, Elmer K. Corbin, Daeik Kim, Moon J. Kim
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Publication number: 20100066496Abstract: An identification method and identification device are presented employing radio frequency and acoustic wave communication modes. The identification method includes: receiving at an acoustic wave and radio frequency identification device an acoustic wave signal of a first frequency and a radio frequency signal of a second frequency, where the acoustic wave signal and the radio frequency signal are received from an acoustic wave and radio frequency identification reader, and the first frequency and the second frequency are different frequencies; and responding to the receiving by transmitting at least one of an acoustic wave identification (AWID) or a radio frequency identification (RFID) from the acoustic wave and radio frequency identification device.Type: ApplicationFiled: September 15, 2008Publication date: March 18, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Choongyeun CHO, Richard FERRI, Daeik KIM, Jonghae KIM, Moon Ju KIM
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Publication number: 20100060344Abstract: Circuits and methods are provided for facilitating transitioning of a digital circuit from backgate biased standby mode to active mode. The digital circuit includes a semiconductor substrate, multiple n-channel transistors disposed at least partially in one or more p-type wells in the semiconductor substrate, multiple p-channel transistors disposed at least partially in one or more n-type wells in the semiconductor substrate, and a backgate control circuit. The backgate control circuit is electrically coupled to the p-type well(s) and to the n-type well(s) to facilitate transitioning of the multiple n-channel transistors and the multiple p-channel transistors from backgate biased standby mode to active mode by automatically shunting charge from the n-type well(s) to the p-type well(s) until a well voltage threshold is reached indicative of a completed transition of the transistors from backgate biased standby mode to active mode.Type: ApplicationFiled: September 8, 2008Publication date: March 11, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Choongyeun CHO, Daeik KIM, Jonghae KIM, Moon Ju KIM
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Publication number: 20100032814Abstract: Back-end-of-line (BEOL) circuit structures and methods are provided for blocking externally-originating or internally-originating electromagnetic edge interference. One such BEOL circuit structure includes a semiconductor substrate supporting one or more integrated circuits, and multiple BEOL layers disposed over the semiconductor substrate. The multiple BEOL layers extend to an edge of the circuit structure and include at least one vertically-extending conductive pattern disposed adjacent to the edge of the circuit structure. The vertically-extending conductive pattern is defined, at least partially, by a plurality of elements disposed in the multiple BEOL layers. The plurality of elements are uniformly arrayed at the edge of the circuit structure in a first direction or a second direction throughout at least a portion thereof.Type: ApplicationFiled: August 8, 2008Publication date: February 11, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Choongyeun CHO, Daeik KIM, Jonghae KIM, Moon Ju KIM, James Randal MOULIC
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Publication number: 20100019908Abstract: A radio frequency identification (RFID) device and method of fabrication are presented. The RFID device includes an RFID antenna, a capacitor, and an RFID integrated circuit. The RFID antenna includes an elongate conductive trace disposed within an antenna area of the RFID device, and the capacitor includes an elongate capacitive structure for storing power. The elongate capacitive structure is aligned with the elongate conductive trace and embedded within the antenna area of the RFID device. The RFID integrated circuit is electrically coupled to the RFID antenna and to the capacitor, and the capacitor stores power within the antenna area of the RFID device to facilitate RFID integrated circuit functionality.Type: ApplicationFiled: July 24, 2008Publication date: January 28, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Choongyeun CHO, Daeik KIM, Jonghae KIM, Moon Ju KIM
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Publication number: 20090134844Abstract: An apparatus and method for recycling and reusing charge in an electronic circuit. The apparatus includes at least one capacitor coupled to a circuit block in the electronic circuit, the capacitor being configured to collect current charge consumed by the circuit block when set to a charge collection mode, and a voltage level comparator configured to detect a fully charged state when the capacitor is fully charged. Further, the apparatus includes a first electrical switch configured to allow, once the fully charged state is detected, the capacitor to switch to a discharge mode for discharging the current charge collected back into the power supply for reuse by the electrical system and a second switch configured to allow, after the capacitor has fully discharged the current charge collected, the capacitor to switch back to the charge collection mode, such that, the current charge is recycled and reused by the electrical system.Type: ApplicationFiled: November 28, 2007Publication date: May 28, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Choongyeun Cho, Daeik Kim, Jonghae Kim, Moon J. Kim, James R. Moulic
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Publication number: 20090132082Abstract: Sub-100 nanometer semiconductor devices and methods and program products for manufacturing devices are provided, in particular inductors comprising a plurality of spaced parallel metal lines disposed on a dielectric surface and each having width, heights, spacing and cross-sectional areas determined as a function of Design Rule Check rules. For one planarization process rule a metal density ratio of 80% metal to 20% dielectric surface is determined and produced. In one example a sum of metal line spacing gaps is less than a sum of metal line interior sidewall heights. In one aspect at least one of line height, width and line spacing dimensions is selected to optimize one or more chip yield, chip performance, chip manufacturability and inductor Q factor parameters.Type: ApplicationFiled: January 30, 2009Publication date: May 21, 2009Applicant: International Business Machines CorporationInventors: Choongyeun Cho, Daeik Kim, Jonghae Kim, Moon J. Kim, Jean-Olivier Plouchart, Robert E. Trzcinski
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Patent number: 7504705Abstract: Sub-100 nanometer semiconductor devices and methods and program products for manufacturing devices are provided, in particular inductors comprising a plurality of spaced parallel metal lines disposed on a dielectric surface and each having width, heights, spacing and cross-sectional areas determined as a function of Design Rule Check rules. For one planarization process rule a metal density ratio of 80% metal to 20% dielectric surface is determined and produced. In one example a sum of metal line spacing gaps is less than a sum of metal line interior sidewall heights. In one aspect at least one of line height, width and line spacing dimensions is selected to optimize one or more chip yield, chip performance, chip manufacturability and inductor Q factor parameters.Type: GrantFiled: September 29, 2006Date of Patent: March 17, 2009Assignee: International Business Machines CorporationInventors: Choongyeun Cho, Daeik Kim, Jonghae Kim, Moon J. Kim, Jean-Olivier Plouchart, Robert E. Trzcinski
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Publication number: 20080136697Abstract: In a random number generator, a first converter converts a first analog noise signal into a random digital clock signal and a second converter samples a second analog noise signal asynchronous to the first analog noise signal in response to the random digital clock signal and generates a random digital number stream. In one aspect, a random number generator output block samples the second converter random digital number stream in response to the random digital clock signal and generates a random number generator block output. In another aspect a pseudo noise source state machine generates the random digital clock signal in response to a first seed generated from the first analog noise signal, a second seed from process variation digital amplifier, and a past machine state.Type: ApplicationFiled: December 8, 2006Publication date: June 12, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Choongyeun Cho, Dae Ik Kim, Jonghae Kim, Moon J. Kim
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Publication number: 20080099880Abstract: Methods, articles and design structures for capacitance circuits are provided disposing a lower vertical-native capacitor metal layer above a planar front-end-of-line semiconductor base substrate, planar metal bottom plates spaced a bottom plate distance from the base and top plates above the bottom plates spaced a top plate distance from the base defining metal-insulator-metal capacitors, top plate footprints disposed above the base substrate smaller than bottom plate footprints and exposing bottom plate remainder upper lateral connector surfaces; disposing parallel positive port and negative port upper vertical-native capacitor metal layers over and each connected to top plate and bottom plate upper remainder lateral connector surface.Type: ApplicationFiled: January 8, 2008Publication date: May 1, 2008Applicant: International Business Machines CorporationInventors: Choongyeun Cho, Jonghae Kim, Moo Kim, Jean-Olivier Plouchart, Robert Trzcinski
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Publication number: 20080079114Abstract: Sub-100 nanometer semiconductor devices and methods and program products for manufacturing devices are provided, in particular inductors comprising a plurality of spaced parallel metal lines disposed on a dielectric surface and each having width, heights, spacing and cross-sectional areas determined as a function of Design Rule Check rules. For one planarization process rule a metal density ratio of 80% metal to 20% dielectric surface is determined and produced. In one example a sum of metal line spacing gaps is less than a sum of metal line interior sidewall heights. In one aspect at least one of line height, width and line spacing dimensions is selected to optimize one or more chip yield, chip performance, chip manufacturability and inductor Q factor parameters.Type: ApplicationFiled: September 29, 2006Publication date: April 3, 2008Applicant: International Business Machines CorporationInventors: Choongyeun Cho, Daeik Kim, Jonghae Kim, Moon J. Kim, Jean-Olivier Plouchart, Robert E. Trzcinski
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Publication number: 20070267733Abstract: Semiconductor chip capacitance circuits and methods are provided comprising at least two capacitors mounted close to a substrate, wherein each capacitor has a lateral lower conductive plate mounted near enough to the substrate to have extrinsic capacitance greater than an upper plate extrinsic capacitance. One half of lower plates and one half of upper plates are connected to a first port, and a remaining one half of upper plates and lower plates are connected to a second port, the first and second port having about equal extrinsic capacitance from the lower plates. In one aspect, the substrate comprises a front-end-of-line capacitor defining a substrate footprint, and the at least two capacitors are back-end-of-line Metal-Insulator-Metal Capacitors disposed above the footprint. In another aspect, the at least two capacitors are at least four capacitors arrayed in a rectangular array generally parallel to the substrate.Type: ApplicationFiled: May 18, 2006Publication date: November 22, 2007Applicant: International Business Machines CorporationInventors: Choongyeun Cho, Jonghae Kim, Moon Kim, Jean-Olivier Plouchart, Robert Trzcinski