Patents by Inventor Chris Avila
Chris Avila has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9978456Abstract: Techniques are presented to reduce the amount of read disturb on partially written blocks of NAND type non-volatile memory, both for when determining the last written word line in a block and also for data read. In both cases, non-selected word lines that are unwritten or, in the case of finding the last written word line, may be unwritten are biased with a lower read-pass voltage then is typically used. The result of such reads can also be applied to an algorithm for finding the last written word by skipping a varying number of word lines. Performance in a last written page determination can also be improved by use of shorter bit line settling times than for a standard read.Type: GrantFiled: November 17, 2014Date of Patent: May 22, 2018Assignee: SanDisk Technologies LLCInventors: Anubhav Khandelwal, Dana Lee, Abhijeet Manohar, Henry Chin, Gautam Dusija, Daniel Tuers, Chris Avila, Cynthia Hsu
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Patent number: 9965362Abstract: Systems and methods for performing data recovery are disclosed. A controller of a memory system may detect an error at a first page of memory and identify a data keep cache associated with the first page, the data keep cache associated with a primary XOR sum. The controller may further sense data stored at a second page and move the data to a first latch of the memory; sense data stored at a third page such that the data is present in a second latch of the memory; and calculate a restoration XOR sum based on the data of the second page and the data of the third page. The controller may further calculate the data of the first page based on the primary XOR sum and the restoration XOR sum, and restore the data of the first page.Type: GrantFiled: September 14, 2016Date of Patent: May 8, 2018Assignee: SANDISK Technologies LLCInventors: Abhijeet Manohar, Chris Avila
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Patent number: 9910730Abstract: A non-volatile storage system identifies a word line with an open neighbor word line and determines whether data stored in non-volatile memory cells connected to the identified word line has an error condition. If the data does have an error condition, then an attempt is made to fix the data and the open neighbor word line is checked for errors. If the open neighbor word line has errors, then memory cells connected to the open neighbor word line are programmed with pseudo data.Type: GrantFiled: October 21, 2015Date of Patent: March 6, 2018Assignee: SANDISK TECHNOLOGIES LLCInventors: Nian Niles Yang, Chris Avila
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Patent number: 9760307Abstract: An array of non-volatile memory cells includes a first plurality of nonvolatile memory cells and a second plurality of non-volatile memory cells. The first plurality of memory cells, which have first diameters of memory holes, are assigned to store portions of data that are not frequently read. The second plurality of memory cells, which have second diameters of memory holes, are assigned to store portions of data that are frequently read. The first diameters are smaller than the second diameters.Type: GrantFiled: September 22, 2015Date of Patent: September 12, 2017Assignee: SanDisk Technologies LLCInventors: Chris Avila, Yingda Dong, Alexander Kwok-Tung Mak, Steven T. Sprouse
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Patent number: 9741444Abstract: Methods and systems are provided where non-volatile solid state memory may include selected memory cells coupled to a selected word line and proxy memory cells coupled to a proxy word line. The selected memory cells may be non-adjacent to the proxy memory cells and be selected for a read operation. A read proxy voltage may be applied to the proxy word line when data is read from the selected memory cells. A read disturb may be determined based on a difference between a predetermined value stored in the proxy memory cells and a value read from the proxy memory cells.Type: GrantFiled: April 10, 2017Date of Patent: August 22, 2017Assignee: SanDisk Technologies LLCInventors: Philip Reusswig, Harish Singidi, Deepak Raghu, Gautam Dusija, Pao-Ling Koh, Chris Avila
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Patent number: 9721662Abstract: A non-volatile memory system includes a plurality of NAND strings (or other arrangements) that form a monolithic three dimensional memory structure, bit lines, word lines, and one or more control circuits. Multiple NAND strings of the plurality of NAND strings have different select gates connected to different select lines. The multiple NAND strings are connected to a common bit line. The multiple NAND strings are connected to a common word line via their respective different select gates. The one or more control circuits concurrently program multiple memory cells on the multiple NAND strings.Type: GrantFiled: January 13, 2016Date of Patent: August 1, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Nian Niles Yang, Chris Avila
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Publication number: 20170213599Abstract: Methods and systems are provided where non-volatile solid state memory may include selected memory cells coupled to a selected word line and proxy memory cells coupled to a proxy word line. The selected memory cells may be non-adjacent to the proxy memory cells and be selected for a read operation. A read proxy voltage may be applied to the proxy word line when data is read from the selected memory cells. A read disturb may be determined based on a difference between a predetermined value stored in the proxy memory cells and a value read from the proxy memory cells.Type: ApplicationFiled: April 10, 2017Publication date: July 27, 2017Inventors: Philip Reusswig, Harish Singidi, Deepak Raghu, Gautam Dusija, Pao-Ling Koh, Chris Avila
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Publication number: 20170200501Abstract: A non-volatile memory system includes a plurality of NAND strings (or other arrangements) that form a monolithic three dimensional memory structure, bit lines, word lines, and one or more control circuits. Multiple NAND strings of the plurality of NAND strings have different select gates connected to different select lines. The multiple NAND strings are connected to a common bit line. The multiple NAND strings are connected to a common word line via their respective different select gates. The one or more control circuits concurrently program multiple memory cells on the multiple NAND strings.Type: ApplicationFiled: January 13, 2016Publication date: July 13, 2017Applicant: SANDISK TECHNOLOGIES INC.Inventors: Nian Niles Yang, Chris Avila
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Patent number: 9659666Abstract: A non-volatile flash memory has bit lines spanning multiple blocks grouped into columns, where each block is connected along multiple regular columns and one or more redundancy columns. When there is a local column defect, so that the defect is not at the level of the whole block or global column, the portions of a column at an individual block can be remapped to a portion of the same block along a redundant column. Sections of multiple columns from different blocks can be remapped to the same redundancy column. Then a memory block includes a number of independently accessible sub-blocks, the process can also be implemented at the sub-block level. A dynamic, system level implementation is presented.Type: GrantFiled: August 31, 2015Date of Patent: May 23, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Niles Nian Yang, Chris Avila
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Patent number: 9646709Abstract: Methods and systems are provided where non-volatile solid state memory may include selected memory cells coupled to a selected word line and proxy memory cells coupled to a proxy word line. The selected memory cells may be non-adjacent to the proxy memory cells and be selected for a read operation. A read proxy voltage may be applied to the proxy word line when data is read from the selected memory cells. A read disturb may be determined based on a difference between a predetermined value stored in the proxy memory cells and a value read from the proxy memory cells.Type: GrantFiled: September 11, 2015Date of Patent: May 9, 2017Assignee: SanDisk Technologies, LLCInventors: Philip Reusswig, Harish Singidi, Deepak Raghu, Gautam Dusija, Pao-Ling Koh, Chris Avila
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Publication number: 20170116075Abstract: A non-volatile storage system identifies a word line with an open neighbor word line and determines whether data stored in non-volatile memory cells connected to the identified word line has an error condition. If the data does have an error condition, then an attempt is made to fix the data and the open neighbor word line is checked for errors. If the open neighbor word line has errors, then memory cells connected to the open neighbor word line are programmed with pseudo data.Type: ApplicationFiled: October 21, 2015Publication date: April 27, 2017Applicant: SANDISK TECHNOLOGIES INC.Inventors: Nian Niles Yang, Chris Avila
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Publication number: 20170076811Abstract: Methods and systems are provided where non-volatile solid state memory may include selected memory cells coupled to a selected word line and proxy memory cells coupled to a proxy word line. The selected memory cells may be non-adjacent to the proxy memory cells and be selected for a read operation. A read proxy voltage may be applied to the proxy word line when data is read from the selected memory cells. A read disturb may be determined based on a difference between a predetermined value stored in the proxy memory cells and a value read from the proxy memory cells.Type: ApplicationFiled: September 11, 2015Publication date: March 16, 2017Inventors: Philip Reusswig, Harish Singidi, Deepak Raghu, Gautam Dusija, Pao-Ling Koh, Chris Avila
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Patent number: 9589645Abstract: Systems, apparatuses, and methods may be provided that adapt to trim set advancement. Trim set advancement may be a change in trim sets over time. A cell of a semiconductor memory may have a first charge level and be programmed with a first trim set. The cell may be reprogrammed by raising the first charge level to a second charge level that corresponds to the cell programmed with a second trim set.Type: GrantFiled: October 6, 2014Date of Patent: March 7, 2017Assignee: SanDisk Technologies LLCInventors: Gautam Dusija, Chris Avila, Jonathan Hsu, Neil Darragh, Bo Lei
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Publication number: 20170062067Abstract: A non-volatile flash memory has bit lines spanning multiple blocks grouped into columns, where each block is connected along multiple regular columns and one or more redundancy columns. When there is a local column defect, so that the defect is not at the level of the whole block or global column, the portions of a column at an individual block can be remapped to a portion of the same block along a redundant column. Sections of multiple columns from different blocks can be remapped to the same redundancy column. Then a memory block includes a number of independently accessible sub-blocks, the process can also be implemented at the sub-block level. A dynamic, system level implementation is presented.Type: ApplicationFiled: August 31, 2015Publication date: March 2, 2017Inventors: Niles Nian Yang, Chris Avila
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Patent number: 9575829Abstract: A method may be performed in a data storage device that includes a memory and a controller, in response to a request to read data from the memory. The data is located within a first word line of the memory. The method includes accessing the data from the first word line and determining, based on a probability threshold, whether to perform a remedial action with respect to a second word line.Type: GrantFiled: March 13, 2013Date of Patent: February 21, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Nian Niles Yang, Chris Avila, Steven Sprouse, Abhijeet Manohar, Yichao Huang
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Patent number: 9552171Abstract: A number of complimentary techniques for the read scrub process using adaptive counter management are presented. In one set of techniques, in addition to maintaining a cumulative read counter for a block, a boundary word line counter can also be maintained to track the number of reads to most recently written word line or word lines of a partially written block. Another set of techniques used read count threshold values that vary with the number of program/erase cycles that a block has undergone. Further techniques involve setting the read count threshold for a closed (fully written) block based upon the number reads it experienced prior to being closed. These techniques can also be applied at a sub-block, zone level.Type: GrantFiled: October 29, 2014Date of Patent: January 24, 2017Assignee: SanDisk Technologies LLCInventors: Yichao Huang, Chris Avila, Dana Lee, Henry Chin, Deepanshu Dutta, Sarath Puthenthermadam, Deepak Raghu
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Publication number: 20170004052Abstract: Systems and methods for performing data recovery are disclosed. A controller of a memory system may detect an error at a first page of memory and identify a data keep cache associated with the first page, the data keep cache associated with a primary XOR sum. The controller may further sense data stored at a second page and move the data to a first latch of the memory; sense data stored at a third page such that the data is present in a second latch of the memory; and calculate a restoration XOR sum based on the data of the second page and the data of the third page. The controller may further calculate the data of the first page based on the primary XOR sum and the restoration XOR sum, and restore the data of the first page.Type: ApplicationFiled: September 14, 2016Publication date: January 5, 2017Applicant: SanDisk Technologies LLCInventors: Abhijeet Manohar, Chris Avila
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Patent number: 9501400Abstract: In a block-erasable nonvolatile memory array, blocks are categorized as bad blocks, prime blocks, and sub-prime blocks. Sub-prime blocks are identified from their proximity to bad blocks or from testing. Sub-prime blocks are configured for limited operation (e.g. only storing non-critical data, or data copied elsewhere, or using some additional or enhanced redundancy scheme).Type: GrantFiled: November 13, 2013Date of Patent: November 22, 2016Assignee: SanDisk Technologies LLCInventors: Chun Sum Yeung, Jian Chen, Aaron Lee, Abhijeet Manohar, Chris Avila, Dana Lee, Jianmin Huang
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Patent number: 9471419Abstract: Systems and methods for performing data recovery are disclosed. A controller of a memory system may detect an error at a first page of memory and identify a data keep cache associated with the first page, the data keep cache associated with a primary XOR sum. The controller may further sense data stored at a second page and move the data to a first latch of the memory; sense data stored at a third page such that the data is present in a second latch of the memory; and calculate a restoration XOR sum based on the data of the second page and the data of the third page. The controller may further calculate the data of the first page based on the primary XOR sum and the restoration XOR sum, and restore the data of the first page.Type: GrantFiled: March 12, 2013Date of Patent: October 18, 2016Assignee: SanDisk Technologies LLCInventors: Abhijeet Manohar, Chris Avila
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Publication number: 20160141046Abstract: Techniques are presented to reduce the amount of read disturb on partially written blocks of NAND type non-volatile memory, both for when determining the last written word line in a block and also for data read. In both cases, non-selected word lines that are unwritten or, in the case of finding the last written word line, may be unwritten are biased with a lower read-pass voltage then is typically used. The result of such reads can also be applied to an algorithm for finding the last written word by skipping a varying number of word lines. Performance in a last written page determination can also be improved by use of shorter bit line settling times than for a standard read.Type: ApplicationFiled: November 17, 2014Publication date: May 19, 2016Inventors: Anubhav Khandelwal, Dana Lee, Abhijeet Manohar, Henry Chin, Gautam Dusija, Daniel Tuers, Chris Avila, Cynthia Hsu