Abstract: In a charge-storage memory array, memory cells that are programmed to a particular threshold voltage range and have subsequently lost charge have their threshold voltages restored by selectively adding charge to the memory cells. Adding charge only to memory cells with high threshold voltage ranges may sufficiently increase threshold voltages of other memory cells so that they do not require separate addition of charge.

Abstract: A number of complimentary techniques for the read scrub process using adaptive counter management are presented. In one set of techniques, in addition to maintaining a cumulative read counter for a block, a boundary word line counter can also be maintained to track the number of reads to most recently written word line or word lines of a partially written block. Another set of techniques used read count threshold values that vary with the number of program/erase cycles that a block has undergone. Further techniques involve setting the read count threshold for a closed (fully written) block based upon the number reads it experienced prior to being closed. These techniques can also be applied at a sub-block, zone level.

Abstract: A number (Nwl) of programmed word lines in a block of NAND strings is determined by measuring a reference combined current (Iref) in the block when all of the memory cells are in a conductive state. Subsequently, to determine if a word line is a programmed word line, an additional combined current (Iadd) in the block is measured with a demarcation voltage applied to the selected word line. The selected word line is determined to be programmed word lines if Idd is less than Iref by at least a margin. Nwl can be used to adjust an erase-verify test of an erase operation by making the erase-verify test relatively hard to pass when the number is relatively small and relatively easy to pass when the number is relatively large. Or, Nwl can be used to identify a next word line to program in the block.

Abstract: In a three-dimensional nonvolatile memory, when a block erase failure occurs, zones within a block may be separately verified to see if some zones pass verification. Zones that pass may be designated as good zones and may subsequently be used to store user data while bad zones in the same block may be designated as bad and may not be used for subsequent storage of user data.

Abstract: Systems, apparatuses, and methods may be provided that adapt to trim set advancement. Trim set advancement may be a change in trim sets over time. A cell of a semiconductor memory may have a first charge level and be programmed with a first trim set. The cell may be reprogrammed by raising the first charge level to a second charge level that corresponds to the cell programmed with a second trim set.

Abstract: In a three-dimensional nonvolatile memory, when a block erase failure occurs, zones within a block may be separately verified to see if some zones pass verification. Zones that pass may be designated as good zones and may subsequently be used to store user data while bad zones in the same block may be designated as bad and may not be used for subsequent storage of user data.

Abstract: In a nonvolatile memory array, such as a three-dimensional array of charge-storage memory cells, data is scrubbed according to a scheme which weights particular data that is exposed to potentially damaging voltages. Data that may cause damage to other data is moved to a location where such potential damage is reduced.

Abstract: In a Multi Level Cell (MLC) memory array, a burst of data from a host may be written in only lower pages of a block in a rapid manner. Other data from a host may be written in lower and upper pages so that data is more efficiently arranged for long term storage.

Abstract: Non-volatile memory and methods of reading non-volatile memory are provided for managing and reducing read related disturb. Techniques are introduced to reduce read disturb using state-dependent read pass voltages for particular word lines during a read operation. Because of their proximity to a selected word line, adjacent word lines can be biased using state-dependent pass voltages while other unselected word lines are biased using a standard or second set of pass voltages. Generally, each state-dependent pass voltage applied to a word line adjacent to the selected word line is larger than the second set of pass voltages applied to other unselected word lines, although this is not required. Other word lines, may also be biased using state-dependent pass voltages. System-level techniques are provided with or independently of state-dependent pass voltages to further reduce and manage read disturb. Techniques may account for data validity and memory write and erase cycles.

Abstract: A 3D NAND stacked non-volatile memory device, comprising: a string comprising a plurality of non-volatile storage elements, the string comprises a channel and extends vertically through layers of the 3D stacked non-volatile memory device, and the plurality of storage elements are subdivided into different groups based on group assignments, each group of the different groups comprises multiple adjacent storage elements of the plurality of storage elements; and a control circuit in communication with the string, the control circuit, to perform a Pseudo Block Operation Mode.

Abstract: In a three dimensional NAND memory, increased threshold voltages in back gate transistors may cause program failures, particularly along word lines near back gates. When back gate transistor threshold voltages cannot be returned to a desired threshold voltage range then modified program conditions, including increased back gate voltage, may be used to allow programming.

Abstract: Configurable parameters may be used to access NAND flash memory according to schemes that optimize such parameters according to predicted characteristics of memory cells, for example, as a function of certain memory cell device geometry, which may be predicted based on the location of a particular device within a memory array.

Abstract: In a three-dimensional NAND memory in which a block contains multiple separately-selectable sets of strings connected to the same set of bit lines, sets of strings are zoned, and different operating parameters applied to different zones. Operating parameters for a zone are obtained from characterizing a reference set of strings in the zone.

Abstract: In a nonvolatile memory, hybrid blocks are initially written with only lower page data. The hybrid blocks later have middle and upper page data written. For high speed writes, data is written to a hybrid block and two or more Single Level Cell (SLC) blocks. The data from the SLC blocks are copied to the hybrid block at a later time in a folding operation.

Abstract: In a nonvolatile memory, hybrid blocks are initially written with only lower page data. The hybrid blocks later have middle and upper page data written. For high speed writes, data is written to a hybrid block and two or more Single Level Cell (SLC) blocks. The data from the SLC blocks are copied to the hybrid block at a later time in a folding operation.

Abstract: Systems and methods for performing defect detection and data recovery within a memory system are disclosed. A controller of a memory system may receive a command to write data in a memory of the memory system; determine a physical location of the memory that is associated with the data write; write data associated with the data write to the physical location; and store the physical location of the memory that is associated with the data write in a Tag cache. The controller may further identify a data keep cache of a plurality of data keep caches that is associated with the data write based on the physical location of the memory that is associated with the data write; update an XOR sum based on the data of the data write; and store the updated XOR sum in the identified data keep cache.

Abstract: In a Multi Level Cell (MLC) memory array, a burst of data from a host may be written in only lower pages of a block in a rapid manner. Other data from a host may be written in lower and upper pages so that data is more efficiently arranged for long term storage.

Abstract: Layers in a multi-layer memory array are categorized according to likely error rates as predicted from their memory hole diameters. Data to be stored along a word line in a high risk layer is subject to a redundancy operation (e.g. XOR) with data to be stored along a word line in a low risk layer so that the risk of both being bad is low.

Abstract: A data storage device includes a memory and a controller. In a particular embodiment, a method is performed in the data storage device. The method is performed during a read threshold voltage update operation and includes determining a first read threshold voltage of a set of storage elements of a memory according to a first technique and determining a second read threshold voltage of the set of storage elements of the memory according to a second technique. The first read threshold voltage is different from the second read threshold voltage, and the first technique is different from the second technique.

Abstract: During a programming data transfer process in a non-volatile storage system, recording units of data are transferred from a host to a memory device, such as a memory card. For each recording unit, pages of data are arranged in an order such that a page which takes longer to write to a memory array of the memory device is provided before a page which takes less time to write. Overall programming time for the recording unit is reduced since a greater degree of parallel processing occurs. While the page which takes longer to program is being programmed to the memory array, the page which takes less time to program is being transferred to the memory device. After programming is completed, the memory device signals the host to transfer a next recording unit. The pages of data may include lower, middle and upper pages.