Patents by Inventor Christian Jacobi
Christian Jacobi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11775445Abstract: Disclosed herein is a virtual cache and method in a processor for supporting multiple threads on the same cache line. The processor is configured to support virtual memory and multiple threads. The virtual cache directory includes a plurality of directory entries, each entry is associated with a cache line. Each cache line has a corresponding tag. The tag includes a logical address, an address space identifier, a real address bit indicator, and a per thread validity bit for each thread that accesses the cache line. When a subsequent thread determines that the cache line is valid for that thread the validity bit for that thread is set, while not invalidating any validity bits for other threads.Type: GrantFiled: October 13, 2020Date of Patent: October 3, 2023Assignee: International Business Machines CorporationInventors: Markus Helms, Christian Jacobi, Ulrich Mayer, Martin Recktenwald, Johannes C. Reichart, Anthony Saporito, Aaron Tsai
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Patent number: 11762659Abstract: An input/output store instruction is handled. A data processing system includes a system nest communicatively coupled to at least one input/output bus by an input/output bus controller. The data processing system further includes at least a data processing unit including a core, system firmware and an asynchronous core-nest interface. The data processing unit is communicatively coupled to the system nest via an aggregation buffer. The system nest is configured to asynchronously load from and/or store data to an external device which is communicatively coupled to the input/output bus. The data processing unit is configured to complete the input/output store instruction before an execution of the input/output store instruction in the system nest is completed.Type: GrantFiled: September 21, 2021Date of Patent: September 19, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christoph Raisch, Marco Kraemer, Frank Siegfried Lehnert, Matthias Klein, Jonathan D. Bradbury, Christian Jacobi, Brenton Belmar, Peter Dana Driever
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Patent number: 11675513Abstract: A computer-implemented method, according to one embodiment, includes: storing records in an input data buffer, where each of the records include a key which is appended to payload data in the respective record. Moreover, for each of the records: shearing the key associated with the record from the payload data, normalizing the sheared key, and storing the normalized sheared key in a first target area of memory. A determination is made as to whether a size of the payload data in the record is outside a predetermine range, and in response to determining that the size of the payload data in the record is outside the predetermine range, the payload data is stored in a second target area of memory. A data locator is also appended to the normalized sheared key in the first target area of memory to form a sheared record.Type: GrantFiled: August 16, 2021Date of Patent: June 13, 2023Assignee: International Business Machines CorporationInventors: Scott B. Compton, Jeffrey Richard Suarez, Matthew Michael Garcia Pardini, Christian Jacobi, Dominik Steenken, Sri Hari Kolusu, Vicky Vezinaw
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Patent number: 11656871Abstract: An input/output store instruction is handled. A data processing system includes a system nest communicatively coupled to at least one input/output bus by an input/output bus controller. The data processing system further includes at least a data processing unit including a core, system firmware and an asynchronous core-nest interface. The data processing unit is communicatively coupled to the system nest via an aggregation buffer. The system nest is configured to asynchronously load from and/or store data to an external device which is communicatively coupled to the input/output bus. The data processing unit is configured to complete the input/output store instruction before an execution of the input/output store instruction in the system nest is completed.Type: GrantFiled: September 21, 2021Date of Patent: May 23, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christoph Raisch, Marco Kraemer, Frank Siegfried Lehnert, Matthias Klein, Jonathan D. Bradbury, Christian Jacobi, Brenton Belmar, Peter Dana Driever
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Publication number: 20230153244Abstract: A method and a system detects a cache line as a potential or confirmed hot cache line based on receiving an intervention of a processor associated with a fetch of the cache line. The method and system include suppressing an action of operations associated with the hot cache line. A related method and system detect an intervention and, in response, communicates an intervention notification to another processor. An alternative method and system detect a hot data object associated with an intervention event of an application. The method and system can suppress actions of operations associated with the hot data object. An alternative method and system can detect and communicate an intervention associated with a data object.Type: ApplicationFiled: January 13, 2023Publication date: May 18, 2023Inventors: Christian Zoellin, Christian Jacobi, Chung-Lung K. Shum, Martin Recktenwald, Anthony Saporito, Aaron Tsai
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Low-latency, high-availability and high-speed SerDes interface having multiple synchronization modes
Patent number: 11646861Abstract: A computer-implemented method includes using a transmitter to send data from the transmitter through a plurality of lanes to a receiver using a synchronous operation mode that includes sending the data from the transmitter through the plurality of lanes to the receiver in a synchronous transmission manner that relies on an alignment between a transmitter clock frequency and a receiver clock frequency. A synchronous operation performance analysis (SOPA) is performed during the synchronous operation mode. A switch from the synchronous operation mode to an asynchronous operation mode is made based on a result of performing the SOPA. The asynchronous operation mode includes sending the data from the transmitter through the plurality of lanes to the receiver without requiring alignment between the transmitter clock frequency and the receiver clock frequency.Type: GrantFiled: September 24, 2021Date of Patent: May 9, 2023Assignee: International Business Machines CorporationInventors: Patrick James Meaney, Ashutosh Mishra, Paul Allen Ganfield, Christian Jacobi, Logan Ian Friedman, Jentje Leenstra, Glenn David Gilda, Jason Andrew Thompson, Yvonne Hanson Kleppel -
Publication number: 20230115533Abstract: Embodiments of the invention are directed to a computer-implemented method of operating a data transmission system. The data transmission system includes a transmitter and a receiver. The computer-implemented method includes using the transmitter to send serialized data from the transmitter through a plurality of lanes to the receiver. The transmitter sends the serialized data at a first serialization ratio. The receiver is configured to receive and load the serialized data at a second deserialization ratio, wherein the first serialization ration is greater than the second deserialization ratio.Type: ApplicationFiled: September 24, 2021Publication date: April 13, 2023Inventors: Patrick James Meaney, Ashutosh Mishra, Paul Allen Ganfield, Christian Jacobi, Logan Ian Friedman, Jentje Leenstra, Glenn David Gilda, Michael B. Spear
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Patent number: 11620231Abstract: Aspects of the invention include defining one or more processor units having a plurality of caches, each processor unit comprising a processor having at least one cache, and wherein each of the one or more processor units are coupled together by an interconnect fabric, for each of the plurality of caches, arranging a plurality of cache lines into one or more congruence classes, each congruence class comprises a chronology vector, arranging each cache in the plurality of caches into a cluster of caches based on a plurality of scope domains, determining a first cache line to evict based on the chronology vector, and determining a target cache for installing the first cache line based on a scope of the first cache line and a saturation metric associated with the target cache, wherein the scope of the first cache line is determined based on lateral persistence tag bits.Type: GrantFiled: August 20, 2021Date of Patent: April 4, 2023Assignee: International Business Machines CorporationInventors: Ram Sai Manoj Bamdhamravuri, Craig R. Walters, Christian Jacobi, Timothy Bronson, Gregory William Alexander, Hieu T. Huynh, Robert J. Sonnelitter, III, Jason D. Kohl, Deanna P. D. Berger, Richard Joseph Branciforte
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LOW-LATENCY, HIGH-AVAILABILITY AND HIGH-SPEED SERDES INTERFACE HAVING MULTIPLE SYNCHRONIZATION MODES
Publication number: 20230098514Abstract: A computer-implemented method includes using a transmitter to send data from the transmitter through a plurality of lanes to a receiver using a synchronous operation mode that includes sending the data from the transmitter through the plurality of lanes to the receiver in a synchronous transmission manner that relies on an alignment between a transmitter clock frequency and a receiver clock frequency. A synchronous operation performance analysis (SOPA) is performed during the synchronous operation mode. A switch from the synchronous operation mode to an asynchronous operation mode is made based on a result of performing the SOPA. The asynchronous operation mode includes sending the data from the transmitter through the plurality of lanes to the receiver without requiring alignment between the transmitter clock frequency and the receiver clock frequency.Type: ApplicationFiled: September 24, 2021Publication date: March 30, 2023Inventors: Patrick James Meaney, Ashutosh Mishra, Paul Allen Ganfield, Christian Jacobi, Logan Ian Friedman, Jentje Leenstra, Glenn David Gilda, Jason Andrew Thompson, Yvonne Hanson Kleppel -
Patent number: 11593107Abstract: An input/output store instruction is handled. A data processing system includes a system nest coupled to at least one input/output bus by an input/output bus controller. The data processing system further includes at least a data processing unit including a core, system firmware and an asynchronous core-nest interface. The data processing unit is coupled to the system nest via an aggregation buffer. The system nest is configured to asynchronously load from and/or store data to at least one external device which is coupled to the at least one input/output bus. The data processing unit is configured to complete the input/output store instruction before an execution of the input/output store instruction in the system nest is completed. The asynchronous core-nest interface includes an input/output status array with multiple input/output status buffers. The system firmware includes a retry buffer and the core includes an analysis and retry logic.Type: GrantFiled: June 18, 2021Date of Patent: February 28, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christoph Raisch, Marco Kraemer, Frank Siegfried Lehnert, Matthias Klein, Jonathan D. Bradbury, Christian Jacobi, Brenton Belmar, Peter Dana Driever
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Publication number: 20230054424Abstract: Aspects of the invention include defining one or more processor units having a plurality of caches, each processor unit comprising a processor having at least one cache, and wherein each of the one or more processor units are coupled together by an interconnect fabric, for each of the plurality of caches, arranging a plurality of cache lines into one or more congruence classes, each congruence class comprises a chronology vector, arranging each cache in the plurality of caches into a cluster of caches based on a plurality of scope domains, determining a first cache line to evict based on the chronology vector, and determining a target cache for installing the first cache line based on a scope of the first cache line and a saturation metric associated with the target cache, wherein the scope of the first cache line is determined based on lateral persistence tag bits.Type: ApplicationFiled: August 20, 2021Publication date: February 23, 2023Inventors: Ram Sai Manoj BAMDHAMRAVURI, Craig R. WALTERS, Christian JACOBI, Timothy BRONSON, Gregory William ALEXANDER, Hieu T. HUYNH, Robert J. SONNELITTER, III, Jason D. KOHL, Deanna P. D. BERGER, Richard Joseph BRANCIFORTE
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Patent number: 11586542Abstract: A method and a system detects a cache line as a potential or confirmed hot cache line based on receiving an intervention of a processor associated with a fetch of the cache line. The method and system include suppressing an action of operations associated with the hot cache line. A related method and system detect an intervention and, in response, communicates an intervention notification to another processor. An alternative method and system detect a hot data object associated with an intervention event of an application. The method and system can suppress actions of operations associated with the hot data object. An alternative method and system can detect and communicate an intervention associated with a data object.Type: GrantFiled: April 9, 2021Date of Patent: February 21, 2023Assignee: International Business Machines CorporationInventors: Christian Zoellin, Christian Jacobi, Chung-Lung K. Shum, Martin Recktenwald, Anthony Saporito, Aaron Tsai
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Publication number: 20230047349Abstract: A computer-implemented method, according to one embodiment, includes: storing records in an input data buffer, where each of the records include a key which is appended to payload data in the respective record. Moreover, for each of the records: shearing the key associated with the record from the payload data, normalizing the sheared key, and storing the normalized sheared key in a first target area of memory. A determination is made as to whether a size of the payload data in the record is outside a predetermine range, and in response to determining that the size of the payload data in the record is outside the predetermine range, the payload data is stored in a second target area of memory. A data locator is also appended to the normalized sheared key in the first target area of memory to form a sheared record.Type: ApplicationFiled: August 16, 2021Publication date: February 16, 2023Inventors: Scott B. Compton, Jeffrey Richard Suarez, Matthew Michael Garcia Pardini, Christian Jacobi, Dominik Steenken, Sri Hari Kolusu, Vicky Vezinaw
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Patent number: 11579874Abstract: An input/output store instruction is handled. A data processing system includes a system nest coupled to at least one input/output bus by an input/output bus controller. The data processing system further includes at least a data processing unit including a core, system firmware and an asynchronous core-nest interface. The data processing unit is coupled to the system nest via an aggregation buffer. The system nest is configured to asynchronously load from and/or store data to at least one external device which is coupled to the at least one input/output bus. The data processing unit is configured to complete the input/output store instruction before an execution of the input/output store instruction in the system nest is completed. The asynchronous core-nest interface includes an input/output status array with multiple input/output status buffers.Type: GrantFiled: June 22, 2021Date of Patent: February 14, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christoph Raisch, Marco Kraemer, Frank Siegfried Lehnert, Matthias Klein, Jonathan D. Bradbury, Christian Jacobi, Peter Dana Driever, Brenton Belmar
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Patent number: 11520659Abstract: A computer-implemented method includes refreshing a set of memory channels in a memory system substantially simultaneously, each memory channel refreshing a rank that is distinct from each of the other ranks being refreshed. Further, the method includes marking a memory channel from the set of memory channels as being unavailable for the rank being refreshed in the memory channel. In one or more examples, the method further includes blocking a fetch command to the memory channel for the rank being refreshed in the memory channel.Type: GrantFiled: January 13, 2020Date of Patent: December 6, 2022Assignee: International Business Machines CorporationInventors: Patrick James Meaney, Glenn David Gilda, David D. Cadigan, Christian Jacobi, Lawrence Jones, Stephen J. Powell
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Patent number: 11513704Abstract: A computer-implemented method, according to one embodiment, includes: processing records by, for each of the records: shearing the key associated with the record from the payload data, normalizing the sheared key, and storing the normalized sheared key in a first target area of memory. A determination is made whether a size of the payload data is outside a first predetermined range. In response to determining that the size of the payload data is outside the first predetermined range, the payload data is stored in a second target area of memory, and a data locator is appended to the normalized sheared key. Furthermore, in response to determining that a storage capacity of the memory is outside a second predetermined range, some of the payload data is transferred to external physical storage. Moreover, an external list is integrated with each of the data locators that correspond to the transferred payload data.Type: GrantFiled: August 16, 2021Date of Patent: November 29, 2022Assignee: International Business Machines CorporationInventors: Scott B. Compton, Jeffrey Richard Suarez, Matthew Michael Garcia Pardini, Christian Jacobi
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Publication number: 20220308906Abstract: Method and system are provided for running a smaller memory-address width program in a larger memory-address width address space. The method includes: dividing a smaller memory-address width program executable code into a set of portions; reserving a first virtual storage area in a part of an address space accessed using a smaller memory-address width address; and reserving a set of second virtual storage areas in a part of the address space accessed using a larger memory-address width address to accommodate the program executable code. The method provides a relocation mechanism to relocate a processor thread by translating using a relocation factor from an address in the reserved first virtual storage area to the one of the reserved second virtual storage areas containing the executable code.Type: ApplicationFiled: March 25, 2021Publication date: September 29, 2022Inventors: Stephen James Hobson, Catherine Mary Moxey, Christian Jacobi, Elpida Tzortzatos
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Patent number: 11403222Abstract: Disclosed herein is a method for operating access to a cache memory via an effective address comprising a tag field and a cache line index field. The method comprises: splitting the tag field into a first group of bits and a second group of bits. The line index bits and the first group of bits are searched in the set directory. A set identifier is generated indicating the set containing the respective cache line of the effective address. The set identifier, the line index bits and the second group of bits are searched in the validation directory. In response to determining the presence of the cache line in the set based on the second searching, a hit signal is generated.Type: GrantFiled: October 13, 2020Date of Patent: August 2, 2022Assignee: International Business Machines CorporationInventors: Christian Jacobi, Ulrich Mayer, Martin Recktenwald, Anthony Saporito, Aaron Tsai
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Patent number: 11379228Abstract: An example design structure tangibly embodied in a machine readable medium includes a first arithmetic logic unit (ALU) to perform fixed point instructions using at least two general registers to read data from a first and second general register of a plurality of general registers and write a result in at least a third general register of the plurality of general registers. The design structure includes a second ALU to perform non-updating fixed point instructions using at least two general registers to only read data from the general registers. The design structure includes an efficiency logic unit coupled to the first ALU and the second ALU. The efficiency logic unit is to receive an instruction and determine whether the received instruction is an updating fixed point instruction or a non-updating fixed point instruction based on a number of general registers to be used to execute the received instruction.Type: GrantFiled: October 16, 2019Date of Patent: July 5, 2022Assignee: International Business Machines CorporationInventors: Avraham Ayzenfeld, Lee E. Eisen, Brian W. Curran, Christian Jacobi
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Patent number: 11366759Abstract: Processing of a storage operand request identified as restrained is selectively, temporarily suppressed. The processing includes identifying a storage operand request as restrained, where the identifying includes obtaining, by a processing unit, an access intent instruction indicating an access intent associated with an operand of a next sequential instruction. The access intent indicates usage of the storage operand request is restrained. Further, the method includes determining whether a storage operand request is to a common storage location shared by multiple processing units of a computing environment and is identified restrained, and based on determining that the storage operand request is restrained, then temporarily suppressing requesting access to the common storage location pursuant to the storage operand request.Type: GrantFiled: December 10, 2020Date of Patent: June 21, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bruce C. Giamei, Christian Jacobi, Daniel V. Rosa, Anthony Saporito, Donald W. Schmidt, Chung-Lung K. Shum