Patents by Inventor Christian Jacobi
Christian Jacobi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10963380Abstract: A simultaneous multithread (SMT) processor having a shared dispatch pipeline includes a first circuit that detects a cache miss thread. A second circuit determines a first cache hierarchy level at which the detected cache miss occurred. A third circuit determines a Next To Complete (NTC) group in the thread and a plurality of additional groups (X) in the thread. The additional groups (X) are dynamically configured based on the detected cache miss. A fourth circuit determines whether any groups in the thread are younger than the determined NTC group and the plurality of additional groups (X), and flushes all the determined younger groups from the cache miss thread.Type: GrantFiled: April 2, 2019Date of Patent: March 30, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gregory W. Alexander, Brian D. Barrick, Thomas W. Fox, Christian Jacobi, Anthony Saporito, Somin Song, Aaron Tsai
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Patent number: 10956337Abstract: Processing of a storage operand request identified as restrained is selectively, temporarily suppressed. The processing includes determining whether a storage operand request to a common storage location shared by multiple processing units of a computing environment is restrained, and based on determining that the storage operand request is restrained, then temporarily suppressing requesting access to the common storage location pursuant to the storage operand request. The processing unit performing the processing may proceed with processing of the restrained storage operand request, without performing the suppressing, where the processing can be accomplished using cache private to the processing unit. Otherwise the suppressing may continue until an instruction, or operation of an instruction, associated with the storage operand request is next to complete.Type: GrantFiled: September 5, 2019Date of Patent: March 23, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bruce C. Giamei, Christian Jacobi, Daniel V. Rosa, Anthony Saporito, Donald W. Schmidt, Chung-Lung K. Shum
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Patent number: 10956341Abstract: An address translation facility is provided for multiple virtualization levels, where a guest virtual address may be translated to a guest non-virtual address, the guest non-virtual address corresponding without translation to a host virtual address, and the host virtual address may be translated to a host non-virtual address, where translation within a virtualization level may be specified as a sequence of accesses to address translation tables. The address translation facility may include a first translation engine and a second translation engine, where the first and second translation engines each have capacity to perform address translation within a single virtualization level of the multiple virtualization levels.Type: GrantFiled: January 27, 2020Date of Patent: March 23, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Uwe Brandt, Markus Helms, Christian Jacobi, Markus Kaltenbach, Thomas Koehler, Frank Lehnert
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Patent number: 10956156Abstract: A Conditional Transaction End (CTEND) instruction is provided that allows a program executing in a nonconstrained transactional execution mode to inspect a storage location that is modified by either another central processing unit or the Input/Output subsystem. Based on the inspected data, transactional execution may be ended or aborted, or the decision to end/abort may be delayed, e.g., until a predefined event occurs. For instance, when the instruction executes, the processor is in a nonconstrained transaction execution mode, and the transaction nesting depth is one at the beginning of the instruction, a second operand of the instruction is inspected, and based on the inspected data, transaction execution may be ended or aborted, or the decision to end/abort may be delayed, e.g., until a predefined event occurs, such as the value of the second operand becomes a prespecified value or a time interval is exceeded.Type: GrantFiled: June 12, 2019Date of Patent: March 23, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dan F. Greiner, Christian Jacobi, Marcel Mitran, Donald W. Schmidt, Timothy J. Slegel
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Patent number: 10956168Abstract: A computer data processing system includes an instruction pipeline having a front end and a back end, a decoding and dispatch unit to dispatch a current instruction; and a pipeline by-pass unit to invoke an out-of-order pipeline by-pass operation. The pipeline by-pass unit by-passes a section of the instruction pipeline such that the current instruction architecturally completes before initiating instruction execution. The computer data processing system further includes a post-completion execution unit that executes the current instruction after the current instruction architecturally completes.Type: GrantFiled: March 8, 2019Date of Patent: March 23, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Avery Francois, Christian Jacobi, Gregory William Alexander
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Patent number: 10949212Abstract: Saving and restoring machine state between multiple executions of an instruction. A determination is made that processing of an operation of an instruction executing on a processor has been interrupted prior to completion. Based on determining that the processing of the operation has been interrupted, current metadata of the processor is extracted. The metadata is stored in a location associated with the instruction and used to re-execute the instruction to resume forward processing of the instruction from where it was interrupted.Type: GrantFiled: July 20, 2020Date of Patent: March 16, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bruce C. Giamei, Martin Recktenwald, Donald W. Schmidt, Timothy Siegel, Aditya N. Puranik, Mark S. Farrell, Christian Jacobi, Jonathan D. Bradbury, Christian Zoellin
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Patent number: 10936283Abstract: A logic device includes a compare unit at one level of a plurality of levels of a hierarchical structure to be used in sorting of records. The compare unit includes a buffer pair in which one or more buffers of the buffer pair are adapted to store at least one record. The logic device further includes another compare unit on another level of the plurality of levels of the hierarchical structure. The other compare unit includes another buffer pair in which one or more other buffers of the other buffer pair are adapted to store a portion of a record. A size of the one or more other buffers of the other buffer pair is insufficient to store the entire record. The one compare unit and the other compare unit are adapted to sort a plurality of records.Type: GrantFiled: November 30, 2017Date of Patent: March 2, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Norbert Hagspiel, Jörg-Stephan Vogt, Christian Jacobi, Matthias Klein
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Patent number: 10929130Abstract: A guarded storage facility sets up a boundary indicating a range of addresses to be guarded or protected. When a program attempts to access an address in a guarded section defined by the boundary, a guarded storage event occurs. Use of this facility facilitates performance of certain tasks within a computing environment, including storage reclamation.Type: GrantFiled: June 28, 2019Date of Patent: February 23, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dan F. Greiner, Christian Jacobi, Volodymyr Paprotski, Anthony Saporito, Chung-Lung K. Shum, Timothy J. Slegel
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Patent number: 10929312Abstract: Embodiments include techniques for using a zone-SDID mapping for translation lookaside buffer (TLB) purges, the techniques include receiving a zone purge request, including zone attribute information, and searching for matching zone attribute information in a zone register using the zone purge request. The techniques also include computing, based at least in part on the search, a state descriptor identifier (SDID) vector for each matching zone of the zone register, and reading TLB entries referenced in the zone purge request. The techniques include comparing an SDID of the TLB entry against an SDID specified in the SDID vector, and purging the TLB entries based on the comparison.Type: GrantFiled: May 7, 2019Date of Patent: February 23, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Uwe Brandt, Ute Gaertner, Lisa C. Heller, Markus Helms, Christian Jacobi, Thomas Koehler, Frank Lehnert, Jennifer A. Navarro
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Patent number: 10915547Abstract: Embodiments of the present invention provide systems and methods for increasing the efficiency of data conversion in a coprocessor by using the statistical occurrence of data patterns to convert frequently occurring data patterns in one conversion cycle. In one embodiment, a coprocessor system is disclosed containing a converter engine, which includes a parser and a converter, an input buffer, and a result store. The input buffer is configured to transfer a set of source data to the converter engine, which converts the source data from first code format to a second code format, and sends the converted source data to the result store.Type: GrantFiled: August 9, 2019Date of Patent: February 9, 2021Assignee: International Business Machines CorporationInventors: Markus M. Helms, Christian Jacobi, Aditya N. Puranik, Parminder Singh
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Publication number: 20210026783Abstract: Disclosed herein is a virtual cache and method in a processor for supporting multiple threads on the same cache line. The processor is configured to support virtual memory and multiple threads. The virtual cache directory includes a plurality of directory entries, each entry is associated with a cache line. Each cache line has a corresponding tag. The tag includes a logical address, an address space identifier, a real address bit indicator, and a per thread validity bit for each thread that accesses the cache line. When a subsequent thread determines that the cache line is valid for that thread the validity bit for that thread is set, while not invalidating any validity bits for other threads.Type: ApplicationFiled: October 13, 2020Publication date: January 28, 2021Inventors: Markus Helms, Christian Jacobi, Ulrich Mayer, Martin Recktenwald, Johannes C. Reichart, Anthony Saporito, Aaron Tsai
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Publication number: 20210026771Abstract: Disclosed herein is a method for operating access to a cache memory via an effective address comprising a tag field and a cache line index field. The method comprises: splitting the tag field into a first group of bits and a second group of bits. The line index bits and the first group of bits are searched in the set directory. A set identifier is generated indicating the set containing the respective cache line of the effective address. The set identifier, the line index bits and the second group of bits are searched in the validation directory. In response to determining the presence of the cache line in the set based on the second searching, a hit signal is generated.Type: ApplicationFiled: October 13, 2020Publication date: January 28, 2021Inventors: Christian Jacobi, Ulrich Mayer, Martin Recktenwald, Anthony Saporito, Aaron Tsai
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Patent number: 10901736Abstract: A conditional instruction end facility is provided that allows completion of an instruction to be delayed. In executing the machine instruction, an operand is obtained, and a determination is made as to whether the operand has a predetermined relationship with respect to a value. Based on determining that the operand does not have the predetermined relationship with respect to the value, the obtaining and the determining are repeated. Based on determining that the operand has the predetermined relationship with respect to the value, execution of the instruction is completed.Type: GrantFiled: July 17, 2019Date of Patent: January 26, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dan F. Greiner, Christian Jacobi, Marcel Mitran, Donald W. Schmidt, Timothy J. Slegel
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Patent number: 10896022Abstract: A compare unit includes an array including a plurality of buffer pairs to receive records on one level of a plurality of levels of a hierarchical structure. A comparator is coupled to the array, and the comparator includes one input to receive one beat of one record from one buffer of a selected buffer pair of the plurality of buffer pairs coupled to the comparator. The comparator further includes another input to receive another beat of another record from another buffer of the selected buffer pair, and logic coupled to the one input and the other input to compare the one beat and the other beat to obtain a winner beat of the compare.Type: GrantFiled: November 30, 2017Date of Patent: January 19, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jörg-Stephan Vogt, Norbert Hagspiel, Christian Jacobi, Matthias Klein
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Publication number: 20210011719Abstract: A Sort Lists instruction is provided to perform a sort and/or a merge operation. The instruction is an architected machine instruction of an instruction set architecture and is executed by a general-purpose processor of the computing environment. The executing includes sorting a plurality of input lists to obtain one or more sorted output lists, which are output.Type: ApplicationFiled: September 30, 2020Publication date: January 14, 2021Inventors: Bruce C. Giamei, Martin Recktenwald, Donald W. Schmidt, Timothy Slegel, Aditya N. Puranik, Mark S. Farrell, Christian Jacobi, Jonathan D. Bradbury, Christian Zoellin
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Patent number: 10884754Abstract: Embodiments include load-balancing a plurality of simultaneous threads of a processor. An example method includes computing a minimum group count for a thread from the plurality of threads. The minimum group count indicates a minimum number of groups of instructions to be assigned to the thread. The method further includes computing a maximum allowed group count for the thread. The maximum allowed group count indicates a maximum number of groups of instructions to be assigned to the thread. The method further includes issuing one or more groups of instructions for execution by the thread based on the minimum group count and the maximum allowed group count for the thread.Type: GrantFiled: November 5, 2019Date of Patent: January 5, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gregory W. Alexander, Stephen Duffy, David S. Hutton, Christian Jacobi, Anthony Saporito, Somin Song
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Publication number: 20200409857Abstract: A computer-implemented method for implementing a full space dynamic address translation (“DAT”) structure and a subspace DAT structure is provided. A non-limiting example of the computer-implemented method includes determining, by a processor, that switching between the full space DAT structure and the subspace DAT structure is enabled by examining a bit in a control register. The method determines, by the processor, that there is a new context different from an existing context based on the bit in the control register indicating that switching is enabled, and switches, by the processor, the context of the DAT structures based on determining that the new context is different from the existing context.Type: ApplicationFiled: June 28, 2019Publication date: December 31, 2020Inventors: Elpida Tzortzatos, Steven M. Partlow, Scott B. Compton, Christine Michele Yost, Charles F. Webb, Christian Jacobi
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Publication number: 20200379760Abstract: In one example implementation according to aspects of the present disclosure, a computer-implemented method for executing a load instruction with a timeout includes receiving, by a processing device, the load instruction. The method further includes attempting, by the processing device, to load a lock on a cache line of a memory. The method further includes determining, by the processing device, whether the timeout has expired prior to a successful loading of the lock on the cache line. The method further includes , responsive to determining that the timeout has expired, executing, by the processing device, another instruction instead of loading the lock on the cache line.Type: ApplicationFiled: May 28, 2019Publication date: December 3, 2020Inventors: Christian Jacobi, Matthias Klein, Martin Recktenwald, Anthony Saporito, Robert J. Sonnelitter, III
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Patent number: 10831664Abstract: Disclosed herein is a method for operating access to a cache memory via an effective address comprising a tag field and a cache line index field. The method comprises: splitting the tag field into a first group of bits and a second group of bits. The line index bits and the first group of bits are searched in the set directory. A set identifier is generated indicating the set containing the respective cache line of the effective address. The set identifier, the line index bits and the second group of bits are searched in the validation directory. In response to determining the presence of the cache line in the set based on the second searching, a hit signal is generated.Type: GrantFiled: June 16, 2017Date of Patent: November 10, 2020Assignee: International Business Machines CorporationInventors: Christian Jacobi, Ulrich Mayer, Martin Recktenwald, Anthony Saporito, Aaron Tsai
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Patent number: 10831476Abstract: A delay facility is provided in which program execution may be delayed until a predefined event occurs, such as a comparison of memory locations results in a true condition, a timeout is reached, an interruption is made pending or another condition exists. The delay facility includes one or more compare and delay machine instructions used to delay execution. The one or more compare and delay instructions may include a 32-bit compare and delay (CAD) instruction and a 64-bit compare and delay (CADG) instruction.Type: GrantFiled: October 8, 2018Date of Patent: November 10, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Charles W. Gainey, Jr., Dan F. Greiner, Christian Jacobi, Marcel Mitran, Donald W. Schmidt, Timothy J. Slegel