Abstract: Saving and restoring machine state between multiple executions of an instruction. A determination is made that processing of an operation of an instruction executing on a processor has been interrupted prior to completion. Based on determining that the processing of the operation has been interrupted, current metadata of the processor is extracted. The metadata is stored in a location associated with the instruction and used to re-execute the instruction to resume forward processing of the instruction from where it was interrupted.

Abstract: A Sort Lists instruction is provided to perform a sort and/or a merge operation. The instruction is an architected machine instruction of an instruction set architecture and is executed by a general-purpose processor of the computing environment. The executing includes sorting a plurality of input lists to obtain one or more sorted output lists, which are output.

Abstract: Migration of partially completed instructions. A determination is made that processing of an operation of an instruction executing on a processor has been interrupted prior to completion. The instruction is re-executed on a selected processor to resume forward processing of the instruction. The re-executing includes determining whether model-dependent metadata is to be used by the selected processor in re-executing the instruction. Based on determining the model-dependent metadata is to be used, the model-dependent metadata is used in re-executing the instruction. Based on determining the model-dependent metadata is not to be used, proceeding with re-executing the instruction without using the model-dependent metadata.

Abstract: Saving and restoring machine state between multiple executions of an instruction. A determination is made that processing of an operation of an instruction executing on a processor has been interrupted prior to completion. Based on determining that the processing of the operation has been interrupted, current metadata of the processor is extracted. The metadata is stored in a location associated with the instruction and used to re-execute the instruction to resume forward processing of the instruction from where it was interrupted.

Abstract: Embodiments of the present invention are directed to a computer-implemented method for generating and verifying hardware instruction traces including memory data contents. The method includes initiating an in-memory trace (IMT) data capture for a processor, the IMT data being an instruction trace collected while instructions flow through an execution pipeline of the processor. The method further includes capturing contents of architected registers of the processor by: storing the contents of the architected registers to a predetermined memory location, and causing a load-store unit (LSU) to read contents of the predetermined memory location.

Abstract: Branch prediction in an instruction using a tag orientation predictor (TOP) is described. When a branch instruction is hotly mis-predicted by a hybrid branch predictor, the branch is tracked over a longer time period using the TOP. Once the TOP has collected enough data to confidently predict a branch prediction, the TOP is used to override a branch prediction from the hybrid predictor when the TOP branch prediction.

Abstract: A processor-implemented method is provided. The processor-implemented includes reading, by a processor, an instruction stream by fetching instructions from an instruction cache of the processor. The processor then executes a branch prediction operation based on a context of the instruction stream and an index when one of the instructions includes a branch instruction. The branch prediction operation output a prediction and a context. The processor then compares the context of the instruction stream and the context from the branch prediction operation to determine whether to execute a stop fetch.

Abstract: A computer processor includes a processor cache that obtains tree data from the memory unit indicative of key values that are pre-sorted in a memory unit. A hardware adaptive merge sort accelerator generates a tournament tree based on the key values, and performs a partial tournament sort that compares a selected key value to a plurality of participating key values to define a sorting path. The hardware adaptive merge sort accelerator also determines an overall winning key value of the partial tournament and a runner-up key value located on the sorting path that is a next lowest key value among the participating key values. The remaining key values are compared to the runner-up key value to sort at least one of the remaining key values in sequential order with respect to the overall winning key value and the runner-up key value.

Abstract: A computer processor includes a memory unit that stores key values to be loaded into a partial tournament sort, and a processor cache that obtains tree data from the memory unit indicating the key values. A hardware merge sort accelerator generates a tournament tree based on the key values, and performs a partial tournament sort to store a first portion of tournament results in the processor cache while excluding a second portion of the tournament results from the processor cache.

Abstract: A computer processor includes a memory unit, a processor cache and a hardware merge sort accelerator. The memory unit stores key values to be sequentially sorted. The processor cache obtains tree data from the memory unit indicating the key values. The hardware merge sort accelerator is configured to generate a master tournament tree based on the key values and perform a tournament sort that determines a first winning key value based on the master tournament tree. The hardware merge sort accelerator further speculates a second winning key value based on the master tournament tree. The speculated second winning key value is a next sequential winning key value of the tournament sort.

Abstract: A method and a system detects a cache line as a potential or confirmed hot cache line based on receiving an intervention of a processor associated with a fetch of the cache line. The method and system include suppressing an action of operations associated with the hot cache line. A related method and system detect an intervention and, in response, communicates an intervention notification to another processor. An alternative method and system detect a hot data object associated with an intervention event of an application. The method and system can suppress actions of operations associated with the hot data object. An alternative method and system can detect and communicate an intervention associated with a data object.

Abstract: A computer system includes a first predictor circuit configured to generate a first predictor signal, and a second predictor circuit configured to generate a second predictor signal different from the first predictor signal. The computer system further includes a TIP arbiter configured to receive the first predictor signal and the second predictor signal, and to select one of the first predictor signal or the second predictor signal as a final prediction of a target address for a fetched branch instruction. The selection is based at least in part on a comparison between a branch address of the fetched branch instruction and a stored tag value, along with a counter value stored in the arbiter entry.

Abstract: A method and a system detects a cache line as a potential or confirmed hot cache line based on receiving an intervention of a processor associated with a fetch of the cache line. The method and system include suppressing an action of operations associated with the hot cache line. A related method and system detect an intervention and, in response, communicates an intervention notification to another processor. An alternative method and system detect a hot data object associated with an intervention event of an application. The method and system can suppress actions of operations associated with the hot data object. An alternative method and system can detect and communicate an intervention associated with a data object.

Abstract: A Sort Lists instruction is provided to perform a sort and/or a merge operation. The instruction is an architected machine instruction of an instruction set architecture and is executed by a general-purpose processor of the computing environment. The executing includes sorting a plurality of input lists to obtain one or more sorted output lists, which are output.

Abstract: Saving and restoring machine state between multiple executions of an instruction. A determination is made that processing of an operation of an instruction executing on a processor has been interrupted prior to completion. Based on determining that the processing of the operation has been interrupted, current metadata of the processor is extracted. The metadata is stored in a location associated with the instruction and used to re-execute the instruction to resume forward processing of the instruction from where it was interrupted.

Abstract: Storage accesses for merge operations are minimized. A plurality of records of a plurality of input lists are merged. The merging includes determining that an input list of the plurality of input lists has become empty, and checking, based on determining that the input list has become empty, a control specific for the input list. The control is used to determine how to proceed, such as whether to end merging or continue merging.

Abstract: Migration of partially completed instructions. A determination is made that processing of an operation of an instruction executing on a processor has been interrupted prior to completion. The instruction is re-executed on a selected processor to resume forward processing of the instruction. The re-executing includes determining whether model-dependent metadata is to be used by the selected processor in re-executing the instruction. Based on determining the model-dependent metadata is to be used, the model-dependent metadata is used in re-executing the instruction. Based on determining the model-dependent metadata is not to be used, proceeding with re-executing the instruction without using the model-dependent metadata.

Abstract: A computer processor includes a memory unit that stores key values to be loaded into a partial tournament sort, and a processor cache that obtains tree data from the memory unit indicating the key values. A hardware merge sort accelerator generates a tournament tree based on the key values, and performs a partial tournament sort to store a first portion of tournament results in the processor cache while excluding a second portion of the tournament results from the processor cache.

Abstract: A method, computer program product, and system includes a processor obtaining data including values and generating a value conversion dictionary by applying a parse tree based compression algorithm to the data, where the value conversion dictionary includes dictionary entries that represent the values. The processor obtains a distribution of the values and estimates a likelihood for each based on the distribution. The processor generates a code word to represent each value, a size of each code word is inversely proportional to the likelihood of the word. The processor assigns a rank to each code word, the rank for each represents the likelihood of the value represented by the code word; and based on the rank associated with each code word, the processor reorders each dictionary entry in the value conversion dictionary to associate each dictionary entry with an equivalent rank, the reordered value conversion dictionary comprises an architected dictionary.

Abstract: A method and a system detects a cache line as a potential or confirmed hot cache line based on receiving an intervention of a processor associated with a fetch of the cache line. The method and system include suppressing an action of operations associated with the hot cache line. A related method and system detect an intervention and, in response, communicates an intervention notification to another processor. An alternative method and system detect a hot data object associated with an intervention event of an application. The method and system can suppress actions of operations associated with the hot data object. An alternative method and system can detect and communicate an intervention associated with a data object.