Patents by Inventor Christian Zoellin
Christian Zoellin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190018681Abstract: Embodiments of the present disclosure relate to processing a microprocessor instruction by receiving a microprocessor instruction for processing by a microprocessor, and processing the microprocessor instruction in a multi-cycle operation by acquiring a unit of data having a plurality of ordered bits, where the acquiring is performed by the microprocessor during a first clock cycle, and shifting the unit of data by a number of bits, where the shifting is performed by the microprocessor during a second clock cycle subsequent to the first clock cycle.Type: ApplicationFiled: July 12, 2017Publication date: January 17, 2019Inventors: Eyal Naor, Martin Recktenwald, Christian Zoellin, Aaron Tsai
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Patent number: 10169041Abstract: Embodiments of the present disclosure relate to processing a microprocessor instruction by receiving a microprocessor instruction for processing by a microprocessor, and processing the microprocessor instruction in a multi-cycle operation by acquiring a unit of data having a plurality of ordered bits, where the acquiring is performed by the microprocessor during a first clock cycle, and shifting the unit of data by a number of bits, where the shifting is performed by the microprocessor during a second clock cycle subsequent to the first clock cycle.Type: GrantFiled: December 20, 2017Date of Patent: January 1, 2019Assignee: International Business Machines CorporationInventors: Eyal Naor, Martin Recktenwald, Christian Zoellin, Aaron Tsai
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Publication number: 20180365149Abstract: A method and a system detects a cache line as a potential or confirmed hot cache line based on receiving an intervention of a processor associated with a fetch of the cache line. The method and system include suppressing an action of operations associated with the hot cache line. A related method and system detect an intervention and, in response, communicates an intervention notification to another processor. An alternative method and system detect a hot data object associated with an intervention event of an application. The method and system can suppress actions of operations associated with the hot data object. An alternative method and system can detect and communicate an intervention associated with a data object.Type: ApplicationFiled: June 16, 2017Publication date: December 20, 2018Inventors: Christian Zoellin, Christian Jacobi, Chung-Lung K. Shum, Martin Recktenwald, Anthony Saporito, Aaron Tsai
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Publication number: 20180365151Abstract: A method and a system detects a cache line as a potential or confirmed hot cache line based on receiving an intervention of a processor associated with a fetch of the cache line. The method and system include suppressing an action of operations associated with the hot cache line. A related method and system detect an intervention and, in response, communicates an intervention notification to another processor. An alternative method and system detect a hot data object associated with an intervention event of an application. The method and system can suppress actions of operations associated with the hot data object. An alternative method and system can detect and communicate an intervention associated with a data object.Type: ApplicationFiled: December 6, 2017Publication date: December 20, 2018Inventors: Christian Zoellin, Christian Jacobi, Chung-Lung K. Shum, Martin Recktenwald, Anthony Saporito, Aaron Tsai
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Publication number: 20180365150Abstract: A method and a system detects a cache line as a potential or confirmed hot cache line based on receiving an intervention of a processor associated with a fetch of the cache line. The method and system include suppressing an action of operations associated with the hot cache line. A related method and system detect an intervention and, in response, communicates an intervention notification to another processor. An alternative method and system detect a hot data object associated with an intervention event of an application. The method and system can suppress actions of operations associated with the hot data object. An alternative method and system can detect and communicate an intervention associated with a data object.Type: ApplicationFiled: December 6, 2017Publication date: December 20, 2018Inventors: Christian Zoellin, Christian Jacobi, Chung-Lung K. Shum, Martin Recktenwald, Anthony Saporito, Aaron Tsai
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Publication number: 20180341481Abstract: Embodiments of the present invention are directed to a computer-implemented method for generating and verifying hardware instruction traces including memory data contents. The method includes initiating an in-memory trace (IMT) data capture for a processor, the IMT data being an instruction trace collected while instructions flow through an execution pipeline of the processor. The method further includes capturing contents of architected registers of the processor by: storing the contents of the architected registers to a predetermined memory location, and causing a load-store unit (LSU) to read contents of the predetermined memory location.Type: ApplicationFiled: November 20, 2017Publication date: November 29, 2018Inventors: Jane H. Bartik, CHRISTIAN JACOBI, David Lee, Jang-Soo Lee, Anthony Saporito, Christian Zoellin
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Publication number: 20180341480Abstract: Embodiments of the present invention are directed to a computer-implemented method for generating and verifying hardware instruction traces including memory data contents. The method includes initiating an in-memory trace (IMT) data capture for a processor, the IMT data being an instruction trace collected while instructions flow through an execution pipeline of the processor. The method further includes capturing contents of architected registers of the processor by: storing the contents of the architected registers to a predetermined memory location, and causing a load-store unit (LSU) to read contents of the predetermined memory location.Type: ApplicationFiled: May 23, 2017Publication date: November 29, 2018Inventors: Jane H. Bartik, Christian Jacobi, David Lee, Jang-Soo Lee, Anthony Saporito, Christian Zoellin
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Publication number: 20180231607Abstract: An integrated circuit chip includes at least two integrated circuits, at least three scan chains, and a multiplexor circuitry. Each integrated circuit includes an integrated circuit input port and an integrated circuit output port. The scan chains and the integrated circuits are coupled by default with a series chain having integrated circuits and scan chains alternating each other. The series chain starts with an initial scan chain and ends with the end scan chain. Each scan chain except the initial one includes a first scan chain input port coupled by default with the integrated circuit output port of the respective adjacent integrated circuit. Each scan chain except the end one includes a first scan chain output port coupled by default with the integrated circuit input port of the respective adjacent integrated circuit.Type: ApplicationFiled: April 12, 2018Publication date: August 16, 2018Inventors: Wilhelm Haller, Markus Kaltenbach, Ulrich Krauch, Nicolas Maeding, Christian Zoellin
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Patent number: 10006965Abstract: An integrated circuit chip includes at least two integrated circuits, at least three scan chains, and a multiplexor circuitry. Each integrated circuit includes an integrated circuit input port and an integrated circuit output port. The scan chains and the integrated circuits are coupled by default with a series chain having integrated circuits and scan chains alternating each other. The series chain starts with an initial scan chain and ends with the end scan chain. Each scan chain except the initial one includes a first scan chain input port coupled by default with the integrated circuit output port of the respective adjacent integrated circuit. Each scan chain except the end one includes a first scan chain output port coupled by default with the integrated circuit input port of the respective adjacent integrated circuit.Type: GrantFiled: September 16, 2016Date of Patent: June 26, 2018Assignee: International Business Machines CorporationInventors: Wilhelm Haller, Markus Kaltenbach, Ulrich Krauch, Nicolas Maeding, Christian Zoellin
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Publication number: 20180095729Abstract: An instruction configured to perform a plurality of functions is executed. Based on a function code associated with the instruction having a selected value, one or more inputs of the instruction are checked to determine which one or more functions of the plurality of functions are to be performed. Based on a first input of the one or more inputs having a first value, a function of providing raw entropy is performed, in which the providing of raw entropy includes storing a number of raw random numbers. Further, based on a second input of the one or more inputs having a second value, a function of providing conditioned entropy is provided, in which the providing of conditioned entropy includes storing a number of conditioned random numbers.Type: ApplicationFiled: September 30, 2016Publication date: April 5, 2018Inventors: Dan F. Greiner, Bernd Nerz, Timothy J. Slegel, Tamas Visegrady, Christian Zoellin
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Publication number: 20180097632Abstract: An instruction to be used to produce a message digest for a message is executed. In execution, a padding state control of the instruction is checked to determine whether padding has been performed for the message. If the checking indicates padding has been performed, a first action is performed; and if the checking indicates padding has not been performed, a second action, different from the first action, is performed.Type: ApplicationFiled: September 30, 2016Publication date: April 5, 2018Inventors: Dan F. Greiner, Timothy J. Slegel, Christian Zoellin
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Patent number: 9891272Abstract: A module plate is provided for use with a wafer handler and testing mechanism. The module plate has a diameter equivalent to an integrated circuit wafer and a height equivalent to or less than a height of a module lid associated with each module in a plurality of modules associated with the module plate. The module plate has a plurality of cutouts in the module plate that have a width equivalent to a width of the module lid and at least a length equivalent to a length of the module lid. The height of the module plate is such that, when a test head contacts a module base of each module in a plurality of modules, the module lid contacts a chuck on which the module plate resides during testing of the module thereby providing resistance in order to accurately test the module.Type: GrantFiled: August 27, 2015Date of Patent: February 13, 2018Assignee: International Business Machines CorporationInventors: Martin Eckert, Eckhard Kunigkeit, Quintino L. Trianni, Christian Zoellin
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Patent number: 9885748Abstract: A module plate is provided for use with a wafer handler and testing mechanism. The module plate has a diameter equivalent to an integrated circuit wafer and a height equivalent to or less than a height of a module lid associated with each module in a plurality of modules associated with the module plate. The module plate has a plurality of cutouts in the module plate that have a width equivalent to a width of the module lid and at least a length equivalent to a length of the module lid. The height of the module plate is such that, when a test head contacts a module base of each module in a plurality of modules, the module lid contacts a chuck on which the module plate resides during testing of the module thereby providing resistance in order to accurately test the module.Type: GrantFiled: June 9, 2015Date of Patent: February 6, 2018Assignee: International Business Machines CorporationInventors: Martin Eckert, Eckhard Kunigkeit, Quintino L. Trianni, Christian Zoellin
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Patent number: 9716515Abstract: Modifying a digital data stream that includes immediately consecutive code words of different length by segmenting, based on a certain block grid, the digital data stream. Each block of the block grid includes a fixed number of bits. It is determined whether all bits of the last block associated with the digital data stream are occupied by data of the digital data stream. If not all bits of the last block are occupied, the unoccupied bits of the last block are padded with bits of an end-of-record (EOR) indicator. If all bits of the last block are occupied, attaching an EOR indicator to the digital data stream is skipped.Type: GrantFiled: December 14, 2015Date of Patent: July 25, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Deepankar Bhattacharjee, Jonathan D. Bradbury, Christian Jacobi, Aditya N. Puranik, Christian Zoellin
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Publication number: 20170170844Abstract: Modifying a digital data stream that includes immediately consecutive code words of different length by segmenting, based on a certain block grid, the digital data stream. Each block of the block grid includes a fixed number of bits. It is determined whether all bits of the last block associated with the digital data stream are occupied by data of the digital data stream. If not all bits of the last block are occupied, the unoccupied bits of the last block are padded with bits of an end-of-record (EOR) indicator. If all bits of the last block are occupied, attaching an EOR indicator to the digital data stream is skipped.Type: ApplicationFiled: December 14, 2015Publication date: June 15, 2017Inventors: Deepankar Bhattacharjee, Jonathan D. Bradbury, Christian Jacobi, Aditya N. Puranik, Christian Zoellin
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Patent number: 9680653Abstract: An instruction to perform ciphering and authentication is executed. The executing includes ciphering one set of data provided by the instruction to obtain ciphered data and placing the ciphered data in a designated location. It further includes authenticating an additional set of data provided by the instruction, in which the authenticating generates at least a part of a message authentication tag. The at least a part of the message authentication tag is stored in a selected location.Type: GrantFiled: October 13, 2016Date of Patent: June 13, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jonathan D. Bradbury, Reinhard T. Buendgen, Dan F. Greiner, Christian Jacobi, Volodymyr Paprotski, Aditya N. Puranik, Timothy J. Slegel, Tamas Visegrady, Christian Zoellin
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Patent number: 9679665Abstract: A method including determining a test duration for testing each of a plurality of memory arrays individually coupled to a plurality of array built-in-self test (ABIST) engines, the test duration is equal to a time period required by each of the plurality of ABIST engines to test each of the plurality of memory arrays, determining a corresponding delay value for each of the plurality of ABIST engines, each of the corresponding delay values is based on the test duration for each of the plurality of memory arrays, and consecutively delaying the start of processing of each of the plurality of ABIST engines by providing each of the corresponding delay values to each of a plurality of programmable delay units individually coupled to each of the plurality of ABIST engines, the start of processing of each of the plurality of ABIST engines is delayed by a different corresponding delay value.Type: GrantFiled: October 29, 2014Date of Patent: June 13, 2017Assignee: International Business Machines CorporationInventors: Martin Eckert, Otto A. Torreiter, Christian Zoellin
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Publication number: 20170161362Abstract: A method, computer program product, and system includes a processor obtaining data including values and generating a value conversion dictionary by applying a parse tree based compression algorithm to the data, where the value conversion dictionary includes dictionary entries that represent the values. The processor obtains a distribution of the values and estimates a likelihood for each based on the distribution. The processor generates a code word to represent each value, a size of each code word is inversely proportional to the likelihood of the word. The processor assigns a rank to each code word, the rank for each represents the likelihood of the value represented by the code word; and based on the rank associated with each code word, the processor reorders each dictionary entry in the value conversion dictionary to associate each dictionary entry with an equivalent rank, the reordered value conversion dictionary comprises an architected dictionary.Type: ApplicationFiled: December 3, 2015Publication date: June 8, 2017Inventors: Jonathan D. BRADBURY, Markus HELMS, Christian JACOBI, Aditya N. PURANIK, Christian ZOELLIN
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Publication number: 20170163283Abstract: A method, computer program product, and system includes a processor obtaining data including values and generating a value conversion dictionary by applying a parse tree based compression algorithm to the data, where the value conversion dictionary includes dictionary entries that represent the values. The processor obtains a distribution of the values and estimates a likelihood for each based on the distribution. The processor generates a code word to represent each value, a size of each code word is inversely proportional to the likelihood of the word. The processor assigns a rank to each code word, the rank for each represents the likelihood of the value represented by the code word; and based on the rank associated with each code word, the processor reorders each dictionary entry in the value conversion dictionary to associate each dictionary entry with an equivalent rank, the reordered value conversion dictionary comprises an architected dictionary.Type: ApplicationFiled: July 29, 2016Publication date: June 8, 2017Inventors: Jonathan D. BRADBURY, Markus HELMS, Christian JACOBI, Aditya N. PURANIK, Christian ZOELLIN
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Publication number: 20170003345Abstract: An integrated circuit chip includes at least two integrated circuits, at least three scan chains, and a multiplexor circuitry. Each integrated circuit includes an integrated circuit input port and an integrated circuit output port. The scan chains and the integrated circuits are coupled by default with a series chain having integrated circuits and scan chains alternating each other. The series chain starts with an initial scan chain and ends with the end scan chain. Each scan chain except the initial one includes a first scan chain input port coupled by default with the integrated circuit output port of the respective adjacent integrated circuit. Each scan chain except the end one includes a first scan chain output port coupled by default with the integrated circuit input port of the respective adjacent integrated circuit.Type: ApplicationFiled: September 16, 2016Publication date: January 5, 2017Inventors: Wilhelm Haller, Markus Kaltenbach, Ulrich Krauch, Nicolas Maeding, Christian Zoellin