Abstract: In a process for forming L-shaped sidewall spacers for a conducive line element, such as a gate electrode structure, the sacrificial spacers are formed of a material having a similar etch behavior as the material of the finally obtained L-shaped spacer, thereby improving tool utilization and reducing process complexity compared to conventional processes. In one particular embodiment, a spacer layer stack is provided having a first etch stop layer, a first spacer layer, a second etch stop layer, and a second spacer layer, wherein the first and second spacer layers are comprised of silicon nitride.

Abstract: In a double-spacer or multi-spacer approach to the formation of sophisticated field effect transistors, an upper sidewall portion of a gate electrode may be effectively exposed during recessing of an outer spacer element, since the outer spacer is substantially comprised of the same material as the liner material. Consequently, the anisotropic etch process for recessing the outer sidewall spacer also efficiently removes liner residues on the upper sidewall portion and provides an increased diffusion path for a refractory metal. Additionally, the lateral extension of the silicide regions on the drain and source area may be increased by correspondingly controlling an isotropic etch process for removing oxide residues.

Abstract: Etch uniformity is improved in that a specified material layer to be etched is exposed to an ion beam so as to implant an ion species, wherein at least one implantation parameter is varied in conformity with local etch rates of the specified material layer. In this way, etch non-uniformities, induced by tool non-uniformities and recipe specific characteristics, may be significantly reduced.

Abstract: A technique is disclosed that enables the formation of a highly conductive tungsten-containing substrate contact, wherein a lower portion of the substrate contact is formed prior to the formation of the circuit elements, and wherein an upper portion is formed along with contact plugs connecting to the circuit element in a common manufacturing process.

Abstract: The present invention discloses a technique for controlling a local etch rate in forming multi-level contact openings, for example, in forming substrate contact openings and transistor contact openings of an SOI device. The aspect ratio dependent etch rate is correspondingly adapted by selecting in advance suitable aspect ratios for the contact openings so that the etch front may reach the respective final depth within a limited time interval.

Abstract: A plasma control apparatus, a plasma etch system and a method of controlling plasma parameters in a production process are provided that may be used for performing real time measurements that relate to at least one physical or chemical property of a plasma. Learning data is generated that indicates at least one expected range for process run data. Process run data is received during the production process, wherein the process run data indicates current values of at least one plasma parameter. The plasma parameter of the production process is controlled based on the received process run data and the learning data.

Abstract: A technique is provided that may be used to improve optical endpoint detection in a plasma etch process. A semiconductor structure is manufactured that includes at least one electrical device. The technique is adapted for forming a signal layer on or in a wafer, wherein the signal layer comprises a chemical element that causes a characteristic optical emission when coming into contact with an etch plasma. The chemical element does not have a primary influence on the electrical properties of the electrical device. The signal layer is for use in a plasma etch process to detect a plasma etch endpoint if the characteristic optical emission is detected. The signal layer may be patterned and may be incorporated into a stop layer.

Abstract: A method for differential offset spacer formation suitable for incorporation into manufacturing processes for advanced CMOS-technologies devices is presented. The method comprises forming a first insulative layer overlying a plurality of gate structures, then forming a second insulative layer overlying the first insulative layer. A mask is formed to expose a first portion of the second insulative layer overlying a gate structure of a first transistor type, and to protect a second portion of the second insulative layer overlying a gate structure of a transistor of a second transistor type. The exposed first portion of the second insulative layer overlying the gate structure of the first type is then etched. After etching, the mask is removed, and the exposed second portion of the second insulative layer and the first insulative layer are etched to form differential spacers abutting the gate structures. Endpoint is utilized to halt the spacer etch process.

Abstract: Various methods of fabricating substrate trenches and isolation structures therein are disclosed. In one aspect, a method of fabricating a trench in a substrate is provided. An oxide/nitride stack is formed on the substrate. An opening with opposing sidewalls is plasma etched in the silicon nitride film until a first portion of the oxide film is exposed while second and third portions of the oxide film positioned on opposite sides of the first portion remain covered by first and second portions of the silicon nitride film that project inwardly from the opposing sidewalls. The oxide film is etched for a selected time period in order to expose a portion of the substrate and to define first and second oxide/nitride ledges that project inwardly from the opposing sidewalls. The substrate is etched to form the trench with the first and second oxide/nitride ledges protecting underlying portions of the substrate.