Abstract: A method and apparatus for preventing contamination in a lithographic apparatus including a projection system, including providing the lithographic apparatus including the projection system for imaging an irradiated portion of a mask onto a target portion of a substrate and placing a pellicle over a surface of the projection system to inhibit contamination of the surface.

Abstract: A method of forming a contact in a flash memory device is disclosed. The method increases the depth of focus margin and the overlay margin between the contact and the stacked gate layers. A plurality of stacked gate layers are formed on a semiconductor substrate, wherein each stacked gate layer extends in a predefined direction and is substantially parallel to other stacked gate layers. An interlayer insulating layer is deposited over the plurality of stacked gate layers, and a contact hole is patterned between a first stacked gate layer of the plurality of stacked gate layers and a second stacked gate layer of the plurality of stacked gate layers. The contact hole is formed in an elongated shape, wherein a major axis of the contact hole is substantially parallel to the stacked gate layers. A conductive layer is deposited in the contact hole and excess conductive material is removed.

Abstract: A method of making organic memory cells made of two electrodes with a controllably conductive media between the two electrodes is disclosed. The controllably conductive media contains an organic semiconductor layer that contains a photosensitive compound. The organic semiconductor layer is formed into memory cells using patterning techniques.

Abstract: An exemplary embodiment relates to a mask for integrated circuit fabrication equipment. The mask includes a multilayer film and an amorphous carbon layer above the multilayer film. The multilayer film is at least partially relatively reflective to radiation having a wavelength of less than 70 nanometers.

Abstract: A method for forming a semiconductor device is described. The method comprises forming a first layer over a semiconductor substrate. At least one hole is formed through the first layer. A bottom anti-reflective coating (BARC) layer is formed in the at least one hole. The BARC layer is exposed to an electron beam (e-beam) so that the BARC layer reaches a flow temperature in the at least one hole. An etch is performed to form a trench in the first layer and over the at least one hole, wherein the BARC layer in the at least one hole acts as an etch resistant layer during the etch.

Abstract: A bottom anti-reflective coating comprising an organic polymer layer having substantially no nitrogen and a low compressive stress in relation to a polysilicon layer is employed as the lower layer of a bi-layer antireflective coating/hardmask structure to reduce deformation of a pattern to be formed in a patternable layer. The organic polymer layer is substantially transparent to visible radiation, enabling better detection of alignment marks during a semiconductor device fabrication process and improving overlay accuracy. The organic polymer layer provides excellent step coverage and may be advantageously used in the fabrication of structures such as FinFETs.

Abstract: One aspect of the present invention relates to a system and method for controlling environmental acid scavengers in real time during pattern exposure of a chemically amplified resist-clad wafer. The system includes a semiconductor wafer comprising a chemically amplified resist layer formed over a substrate layer, wherein a first portion of the resist layer has been removed to expose an area of the substrate layer in order to form a probe area; an exposure system programmed to implement an exposure process to transfer a device pattern onto at least a second portion of the resist layer; and a monitoring system adapted to detect chemical signals about the probe area in order to control the integrity of the resist layer during the exposure process. The method involves feeding data back to the on-going exposure process in order to effect an immediate change in the process.

Abstract: An exemplary embodiment relates to a phase shifting mask including a glass substrate layer and an amorphous carbon absorber layer located above the glass substrate layer. The amorphous carbon absorber layer includes apertures through which light passes unaltered to the glass substrate layer.

Abstract: To reduce the width of a MOSFET gate, the gate is formed with a hardmask formed thereupon. An isotropic etch is then performed to trim the gate in order to reduce the width of the gate. The resulting gate may be formed with a width that is narrower than a minimum width achievable solely through conventional projection lithography techniques.

Abstract: The present invention provides systems and methods that facilitate formation of semiconductor devices via planarization processes. The present invention utilizes dishing effects that typically occur during a chemical mechanical planarization (CMP) process. A reducing CMP process is performed on a semiconductor device in order to form a passive layer instead of performing a first CMP, followed by a deposition and a second CMP to form a passive layer. The reducing CMP process utilizes a slurry that includes a reducing chemistry that forms the passive layer in a dish region of an electrode. Thus, the passive layer is formed in conjunction with the reducing CMP process utilized for forming the electrode.

Abstract: A projection lithography system exposes a photo sensitive material on a surface of a semiconductor substrate that includes surface height variations between a high level and a low level. The system comprises an illumination source projecting illumination within a narrow wavelength band centered about a nominal wavelength on an optic path towards the substrate during an exposure period. A wavelength modulation system within the optic path comprises means for chromatically separating the narrow wavelength band into at least two sub-bands, the first sub-band being smaller than the narrow wavelength band and centered about a first sub-band wavelength and the second sub-band being smaller than the narrow wavelength band and centered about a second sub-band wavelength and means for passing each of the first sub-band and the second sub-band during distinct time periods within the exposure period.

Abstract: A method of forming a fuse for use in an integrated circuit using an amorphous carbon mask includes providing a mask material layer comprising amorphous carbon over a conductive layer. The mask material layer is doped with nitrogen, and an anti-reflective coating (ARC) feature is formed over the mask layer. A portion of the mask material layer is removed according to the ARC feature to form a mask, and the ARC feature is removed to form a warped mask. The conductive layer is patterned according to the warped mask, the warped mask is removed, and a silicide layer is provided over the patterned conductive layer.

Abstract: A method of making organic memory cells made of two electrodes with a controllably conductive media between the two electrodes is disclosed. The controllably conductive media contains an organic semiconductor layer that contains a photosensitive compound. The organic semiconductor layer is formed into memory cells using patterning techniques.

Abstract: A systems and methodologies are provided for metal overetch control. Metal overetch processes are controlled by utilizing overetch device models to determine overetch times or overetch endpoints. The systems and methodologies reduce the need for manual testing and manual overetch characterization. An overetch system includes a metal etcher, a target device and an overetch controller. The target device is located in or on the metal etcher. The overetch controller is coupled to the metal etcher. The overetch controller controls overetching of the target device by the metal etcher. The overetch controller includes an overetch time controller, a set of etch control models and a control system.

Abstract: The present invention provides a method to fabricate an organic memory device, wherein the fabrication method includes forming a lower electrode, depositing a passive material over the surface of the lower electrode, applying an organic semiconductor material over the passive material, and operatively coupling the an upper electrode to the lower electrode through the organic semiconductor material and the passive material. Patterning of the organic semiconductor material is achieved by depositing a silicon-based resist over the organic semiconductor, irradiating portions of the silicon-based resist and patterning the silicon-based resist to remove the irradiated portions of the silicon-based resist. Thereafter, the exposed organic semiconductor can be patterned, and the non-irradiated silicon-based resist can be stripped to expose the organic semiconductor material that can be employed as a memory cell for single and multi-cell memory devices.

Abstract: Disclosed are methods for processing a low k material involving providing a low k material layer comprising one or more low k polymer materials and one or more high modulus fillers on a semiconductor substrate, and chemical mechanical polishing the low k material layer so as to remove a portion of the low k material layer from the semiconductor substrate without substantially damaging unremoved portions of the low k material layer. In this connection, low k material layers for a semiconductor structure containing one or more low k polymer materials and one or more high modulus fillers are disclosed, as well as methods of making the low k material layers.

Abstract: One aspect of the present invention relates to a method of fabricating a polymer memory device in a via. The method involves providing a semiconductor substrate having at least one metal-containing layer thereon, forming at least one copper contact in the metal-containing layer, forming at least one dielectric layer over the copper contact, forming at least one via in the dielectric layer to expose at least a portion of the copper contact, forming a polymer material in a lower portion of the via, and forming a top electrode material layer in an upper portion of the via.

Abstract: Methods of making an organic memory cell made of two electrodes with a controllably conductive media between the two electrodes are disclosed. The controllably conductive Media contains an organic semiconductor layer and passive layer. In particular, novel methods of forming a electrode and adjacent passive layer are described.

Abstract: A method for an integrated circuit includes the use of an amorphous carbon ARC mask. A layer of amorphous carbon material is deposited above a layer of conductive material, and a layer of anti-reflective coating (ARC) material is deposited over the layer of amorphous carbon material. The layer of amorphous carbon material and the layer of ARC material are etched to form a mask comprising an ARC material portion and an amorphous carbon portion. A feature may then be formed in the layer of conductive material by etching the layer of conductive material in accordance with the mask.

Abstract: A system for monitoring a fabrication process is provided. The system includes one or more light sources, each light source directing light to one or more gratings on a wafer. Light reflected from the gratings is collected by a measuring system that processes the collected light. The collected light is indicative of distortion due to stress at respective portions of the wafer. The measuring system provides distortion/stress related data to a processor that determines the acceptability of the distortion of the respective portions of the wafer. The collected light may be analyzed by scatterometry systems to produce scatterometry signatures associated with distortion and to produce feed-forward control information that can be employed to control semiconductor fabrication processes.