Abstract: The present invention is directed to a comprehensive design flow system. A system and method are provided that provide a comprehensive system to introduce a metamethodology that integrates EDA design tools into a manageable and predictable design flow. A method of designing an integrated circuit may include accessing a design utility operating on an information handling system, displaying a dynamic template on a display device of an information handling system, wherein the dynamic template implements at least two symbols displayable on a display device, in which the at least two symbols each correspond to a respective EDA tool, and arranging the at least two symbols displayed on the display device. The at least two symbols are arranged to indicate an interrelationship of the EDA tools in a design process of an integrated circuit.

Abstract: An integrated circuit is disclosed for selectively encrypting plaintext data received from a first device to produce encrypted data to send to a second device. The integrated circuit comprises controllable encryption circuitry comprising a data input, an enable input, and a data output. The integrated circuit further comprises a plaintext input for providing the plaintext data to the data input, an encrypted text output for providing the encrypted data from the data output, and a first control input for receiving a first device authentication signal for authenticating the first device. The integrated circuit further comprises a verification circuit responsive to the first device authentication signal for producing a first verification signal for use in controlling the enable input of the encryption circuitry to enable the encryption circuitry to provide the encrypted data via the encrypted text output.

Abstract: A network switch is disclosed for resolving requests from a plurality of host initiators by scheduling access to a plurality of disk storage devices. The network switch comprises a switched fabric comprising a plurality of switching elements. Each switching element comprises a plurality of bi-directional switched fabric ports, and a control input connected to receive switch control data for selectively configuring the switching element in order to interconnect the bi-directional switched fabric ports. The network switch further comprises a memory for storing a routing and scheduling program, and a microprocessor, responsive to the requests, for executing the steps of the routing and scheduling program to generate the switch control data to transmit scheduled requests through the bi-directional switched fabric ports. At least one of the plurality of switching elements comprises a disk storage interface for connecting to a selected one of the disk storage devices.

Abstract: The present invention is directed to a system and method for coevolutionary circuit design. A system suitable for providing integrated circuit design may include a memory suitable for storing a first set of instructions and a second set of instructions and a processor communicatively coupled to the memory. The processor is suitable for performing the first set of instructions and the second set of instructions. The first set of instructions is suitable for configuring a processor to provide an integrated circuit development environment in which a support methodology for an integrated circuit is created. The second set of instructions is suitable for configuring a processor to provide tools for implementing a platform architecture of an integrated circuit in which the platform architecture supplies a structure of the integrated circuit.

Abstract: The present invention is directed to an interactive representation of structural dependencies in semiconductor design flows. In an aspect of the present invention, a method for providing interactive representation of structural dependencies in a semiconductor design flow as implemented by an information handling system may include detecting a modified value of a parameter of the semiconductor design flow. At least one parameter dependent on the changed parameter is identified, the dependent parameter previously entered by a user.

Abstract: The present invention is directed to a method and system for optimally mapping a general set of resources to a specific integrated circuit design. In an exemplary aspect of the present invention, a method for optimally mapping a general set of resources to a specific integrated circuit design may include the following steps. Sets of transistors are first abstracted into abstracted resources. The abstracted resources may include a transformative resource, a coordinating resource, and a state management resource, and the like. Then, a sea-of-platforms is utilized for unifying a flexible and malleable collection of the abstracted resources in such a way as to optimize the abstracted resources for a specific integrated circuit design. Broken symmetry may be used to optimize the abstracted resources for the specific integrated circuit design. The broken symmetry may be in at least one of a physical 3-dimensional space, a temporal space and a code space.

Abstract: The present invention is directed to magnetoresistive memory and data storage devices. A system for providing distributed functionality in an electronic environment includes a plurality of platforms suitable for providing a logic function. The platforms include embedded programmable logic, and MRAM memory, the logic and MRAM memory communicatively coupled via an interconnect.

Abstract: A device is disclosed comprising encryption circuitry for encrypting plaintext data into ciphertext data. A memory stores an initial spectral signature representing an initial spectral characteristic of the device, and a signal generator for generating an operating spectral signature representing an operating spectral characteristic of the device. A comparator compares the operating spectral signature to the initial spectral signature and enables the encryption circuitry if the operating spectral characteristic substantially matches the initial spectral characteristic.

Abstract: The present invention provides a comprehensive design environment defining a system architecture and methodology that may integrate interconnects, cores, ePLC, re-configurable processors and software into a manageable and predictable system designs that achieve on-time system IC design results meeting desired specifications and budgets. For example, an interscalable interconnect maybe provided that is scalable and isochronous capable. Additionally, an abstract language may be provided to be able to describe interconnecting core functions. Further, a self-programmable chip may be provided that, upon receiving a construct, it could program itself to achieve the desired functionality, such as through the use of on-chip knowledge and the like.

Abstract: An architecture is described having characteristics, scale and realized according to a minimized cost function with the ability to control and govern liability, availability, band width, capacity and quality of service as one pleases subject to a desired type of management software or framework.

Abstract: The present invention provides a comprehensive design environment defining a system architecture and methodology that may integrate interconnects, cores, ePLC, re-configurable processors and software into a manageable and predictable system designs that achieve on-time system IC design results meeting desired specifications and budgets. For example, an interscalable interconnect maybe provided that is scalable and isochronous capable. Additionally, an abstract language may be provided to be able to describe interconnecting core functions. Further, a self-programmable chip may be provided that, upon receiving a construct, it could program itself to achieve the desired functionality, such as through the use of on-chip knowledge and the like.

Abstract: The present invention is directed to magnetoresistive memory and data storage devices. A system for providing distributed functionality in an electronic environment includes a plurality of platforms suitable for providing a logic function. The platforms include embedded programmable logic, and MRAM memory, the logic and MRAM memory communicatively coupled via an interconnect.

Abstract: The present invention is directed to a disk drive which can assert control over the information content supplied in response to a read request from the host by performing a selective translation of addresses received from the host. The disk drive can include hardware, firmware, or a combination thereof, to unambiguously detect a command block to read a predetermined location on the drive. The drive, upon detecting occurrence of a predetermined address included in the command block, translates the address to initiate a read from an alternate, substitute location information stored at the substitute location is returned to the requesting host in satisfaction of the host's request. The information can be blocks of data, such as audio/video data, or can be executable code including, but not limited to, code used to boot a substitute operating system stored at a location known only to the drive.

Abstract: The present invention is directed to a scale-invariant topology and traffic allocation in multi-node system-on-chip switching fabrics. A method for allocating resources in a design of an integrated circuit may include receiving resource data for components of an integrated circuit. The resource data is suitable for indicating consumption by the components of at least one resource. Integrated circuit resources for the components of the integrated circuit are allocated according to a power law distribution as applied to the received resource data.

Abstract: The present invention is directed to platform architecture used for integrated circuit design. A system for providing distributed dynamic functionality in an electronic environment may include a plurality of platforms. The platforms are suitable for providing a logic function, and include embedded programmable logic, memory and a reconfigurable core. The logic, memory and reconfigurable core are communicatively coupled via a fabric interconnect. A map is also included which expresses logic functions of the plurality of platforms.

Abstract: The present invention provides a comprehensive design environment defining a system architecture and methodology that may integrate interconnects, cores, ePLC, re-configurable processors and software into a manageable and predictable system designs that achieve on-time system IC design results meeting desired specifications and budgets. For example, an interscalable interconnect maybe provided that is scalable and isochronous capable. Additionally, an abstract language may be provided to be able to describe interconnecting core functions. Further, a self-progrmnmable chip may be provided that, upon receiving a construct, it could program itself to achieve the desired functionality, such as through the use of on-chip knowledge and the like.

Abstract: A disk drive comprising a disk for storing encrypted data is disclosed. The disk drive comprises a first circuit for providing plaintext data to a second circuit. The second circuit comprises controllable encryption circuitry for encrypting the plaintext data into the encrypted data. The controllable encryption circuitry comprises a data input, an enable input, and a data output. The second circuit further comprises a plaintext input for providing the plaintext data to the data input, an encrypted text output for providing the encrypted data from the data output, and a first control input for receiving a first device authentication signal for authenticating the first circuit. The second circuit comprises a first verification circuit, responsive to the first device authentication signal, for producing a first verification signal for use in controlling the enable input of the encryption circuitry to enable the encryption circuitry to provide the encrypted data via the encrypted text output.

Abstract: The present invention pertains to a system and method for specifying links, connectivity and bandwidth in an interconnect fabric. For example, a method for allocating connectivity and bandwidth of an integrated circuit may include receiving an interconnect fabric description, the described interconnect fabric having a plurality of platforms linked over an isochronous interconnect fabric. An arrangement of links of the received interconnect fabric is virtualized based on bandwidth. An arrangement of links of the received interconnect fabric is virtualized based on connectivity. The links are allocated on the basis of the virtualized link arrangements based on bandwidth and connectivity.

Abstract: Exemplary embodiments of the present invention are directed to a data storage device and associated method for reproducing a stored data stream with at least one data storage media having addressable storage locations storing data segments and pointers. The data segments define the stored data stream, and the pointers indicate addressable storage locations for other segments in the stored data stream. Each pointer includes a field for identifying whether the data stored includes the addressable storage location of the segment indicated by the pointer. A controller is responsive to the data segments for reproducing a stored data stream in accordance with an autonomously-defined sequence determined by the pointers.

Abstract: A switched node is disclosed for use in a switched fabric network. The switched node comprises a disk and a head actuated over the disk. An integrated disk controller within the switched node comprises more than two bi-directional ports for simultaneously transmitting data in multiple directions through the switched fabric network, each port comprising an input port and an output port. The disk controller circuitry further comprises interface circuitry for interfacing with the head, a data buffer for storing data received from the input ports and data received from the head via the interface circuitry, and routing circuitry responsive to header data received from the input ports and header data received from the interface circuitry.