Patents by Inventor Christopher P. D'Emic
Christopher P. D'Emic has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8917096Abstract: A mechanism is provided for determining an isoelectric point of a molecule. A first group of capacitance versus voltage curves of a capacitor is measured. The capacitor includes a substrate, dielectric layer, and conductive solution. The first group of curves is measured for pH values of the solution without the molecule bound to a functionalized material on the dielectric layer of the capacitor. A second group of capacitance versus voltage curves of the capacitor is measured when the molecule is present in the solution, where the molecule is bound to the functionalized material of the dielectric layer of the capacitor. A shift is determined in the second group of curves from the first group of curves at each pH value. The isoelectric point of the molecule is determined by extrapolating a pH value corresponding to a shift voltage being zero, when the shift is compared to the pH values.Type: GrantFiled: November 15, 2012Date of Patent: December 23, 2014Assignee: International Business Machines CorporationInventors: Ali Afzali-Ardakani, Christopher P. D'Emic, Ashish Jagtiani, Sufi Zafar
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Publication number: 20140175522Abstract: An apparatus comprises: a sensing element formed on a buried oxide layer of a substrate and providing communication between a source region and a drain region; a gate dielectric layer on the sensing element, the gate dielectric layer defining a sensing surface on the sensing element; a passive surface surrounding the sensing surface; and a compound bound to the sensing surface and not bound to the passive surface, the compound having a ligand specifically configured to preferentially bind a target molecule to be sensed. An electrolyte solution in contact with the sensing surface and the passive surface forms a top gate of the apparatus.Type: ApplicationFiled: December 21, 2012Publication date: June 26, 2014Applicant: International Business Machines CorporationInventors: Ali Afzali-Ardakani, Christopher P. D'Emic, Ashish Jagtiani, Sufi Zafar
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Publication number: 20140179047Abstract: An apparatus comprises: a sensing element formed on a buried oxide layer of a substrate and providing communication between a source region and a drain region; a gate dielectric layer on the sensing element, the gate dielectric layer defining a sensing surface on the sensing element; a passive surface surrounding the sensing surface; and a compound bound to the sensing surface and not bound to the passive surface, the compound having a ligand specifically configured to preferentially bind a target molecule to be sensed. An electrolyte solution in contact with the sensing surface and the passive surface forms a top gate of the apparatus.Type: ApplicationFiled: August 13, 2013Publication date: June 26, 2014Applicant: International Business Machines CorporationInventors: Ali Afzali-Ardakani, Christopher P. D'Emic, Ashish Jagtiani, Sufi Zafar
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Publication number: 20140132276Abstract: A mechanism is provided for determining an isoelectric point of a molecule. A first group of capacitance versus voltage curves of a capacitor is measured. The capacitor includes a substrate, dielectric layer, and conductive solution. The first group of curves is measured for pH values of the solution without the molecule bound to a functionalized material on the dielectric layer of the capacitor. A second group of capacitance versus voltage curves of the capacitor is measured when the molecule is present in the solution, where the molecule is bound to the functionalized material of the dielectric layer of the capacitor. A shift is determined in the second group of curves from the first group of curves at each pH value. The isoelectric point of the molecule is determined by extrapolating a pH value corresponding to a shift voltage being zero, when the shift is compared to the pH values.Type: ApplicationFiled: August 20, 2013Publication date: May 15, 2014Applicant: International Business Machines CorporationInventors: Ali Afzali-Ardakani, Christopher P. D'Emic, Ashish Jagtiani, Sufi Zafar
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Publication number: 20140132275Abstract: A mechanism is provided for determining an isoelectric point of a molecule. A first group of capacitance versus voltage curves of a capacitor is measured. The capacitor includes a substrate, dielectric layer, and conductive solution. The first group of curves is measured for pH values of the solution without the molecule bound to a functionalized material on the dielectric layer of the capacitor. A second group of capacitance versus voltage curves of the capacitor is measured when the molecule is present in the solution, where the molecule is bound to the functionalized material of the dielectric layer of the capacitor. A shift is determined in the second group of curves from the first group of curves at each pH value. The isoelectric point of the molecule is determined by extrapolating a pH value corresponding to a shift voltage being zero, when the shift is compared to the pH values.Type: ApplicationFiled: November 15, 2012Publication date: May 15, 2014Applicant: International Business Machines CorporationInventors: Ali Afzali-Ardakani, Christopher P. D'Emic, Ashish Jagtiani, Sufi Zafar
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Patent number: 8586441Abstract: A germanium lateral bipolar junction transistor (BJT) is formed employing a germanium-on-insulator (GOI) substrate. A silicon passivation layer is deposited on the top surface of a germanium layer in the GOI substrate. Shallow trench isolation structures, an extrinsic base region structure, and a base spacer are subsequently formed. A germanium emitter region, a germanium base region, and a germanium collector region are formed within the germanium layer by ion implantation. A silicon emitter region, a silicon base region, and a silicon collector region are formed in the silicon passivation layer. After optional formation of an emitter contact region and a collector contact region, metal semiconductor alloy regions can be formed. A wide gap contact for minority carriers is provided between the silicon base region and the germanium base region and between the silicon emitter region and the germanium emitter region.Type: GrantFiled: September 12, 2012Date of Patent: November 19, 2013Assignee: International Business Machines CorporationInventors: Jin Cai, Kevin K. Chan, Christopher P. D'Emic, Bahman Hekmatshoartabari, Tak H. Ning, Dae-Gyu Park
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Patent number: 8557670Abstract: A lateral heterojunction bipolar transistor is formed on a semiconductor-on-insulator substrate including a top semiconductor portion of a first semiconductor material having a first band gap and a doping of a first conductivity type. A stack of an extrinsic base and a base cap is formed such that the stack straddles over the top semiconductor portion. A dielectric spacer is formed around the stack. Ion implantation of dopants of a second conductivity type is performed to dope regions of the top semiconductor portion that are not masked by the stack and the dielectric spacer, thereby forming an emitter region and a collector region. A second semiconductor material having a second band gap greater than the first band gap and having a doping of the second conductivity type is selectively deposited on the emitter region and the collector region to form an emitter contact region and a collector contact region, respectively.Type: GrantFiled: September 6, 2012Date of Patent: October 15, 2013Assignee: International Business Machines CorporationInventors: Jin Cai, Kevin K. Chan, Christopher P. D'Emic, Tak H. Ning, Dae-Gyu Park
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Patent number: 8558282Abstract: A germanium lateral bipolar junction transistor (BJT) is formed employing a germanium-on-insulator (GOI) substrate. A silicon passivation layer is deposited on the top surface of a germanium layer in the GOI substrate. Shallow trench isolation structures, an extrinsic base region structure, and a base spacer are subsequently formed. A germanium emitter region, a germanium base region, and a germanium collector region are formed within the germanium layer by ion implantation. A silicon emitter region, a silicon base region, and a silicon collector region are formed in the silicon passivation layer. After optional formation of an emitter contact region and a collector contact region, metal semiconductor alloy regions can be formed. A wide gap contact for minority carriers is provided between the silicon base region and the germanium base region and between the silicon emitter region and the germanium emitter region.Type: GrantFiled: September 8, 2012Date of Patent: October 15, 2013Assignee: International Business Machines CorporationInventors: Jin Cai, Kevin K. Chan, Christopher P. D'Emic, Bahman Hekmatshoartabari, Tak H. Ning, Dae-Gyu Park
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Publication number: 20130256757Abstract: A lateral heterojunction bipolar transistor is formed on a semiconductor-on-insulator substrate including a top semiconductor portion of a first semiconductor material having a first band gap and a doping of a first conductivity type. A stack of an extrinsic base and a base cap is formed such that the stack straddles over the top semiconductor portion. A dielectric spacer is formed around the stack. Ion implantation of dopants of a second conductivity type is performed to dope regions of the top semiconductor portion that are not masked by the stack and the dielectric spacer, thereby forming an emitter region and a collector region. A second semiconductor material having a second band gap greater than the first band gap and having a doping of the second conductivity type is selectively deposited on the emitter region and the collector region to form an emitter contact region and a collector contact region, respectively.Type: ApplicationFiled: March 29, 2012Publication date: October 3, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jin Cai, Kevin K. Chan, Christopher P. D'Emic, Tak H. Ning, Dae-Gyu Park
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Publication number: 20130260526Abstract: A lateral heterojunction bipolar transistor is formed on a semiconductor-on-insulator substrate including a top semiconductor portion of a first semiconductor material having a first band gap and a doping of a first conductivity type. A stack of an extrinsic base and a base cap is formed such that the stack straddles over the top semiconductor portion. A dielectric spacer is formed around the stack. Ion implantation of dopants of a second conductivity type is performed to dope regions of the top semiconductor portion that are not masked by the stack and the dielectric spacer, thereby forming an emitter region and a collector region. A second semiconductor material having a second band gap greater than the first band gap and having a doping of the second conductivity type is selectively deposited on the emitter region and the collector region to form an emitter contact region and a collector contact region, respectively.Type: ApplicationFiled: September 6, 2012Publication date: October 3, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jin Cai, Kevin K. Chan, Christopher P. D'Emic, Tak H. Ning, Dae-Gyu Park
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Publication number: 20130049200Abstract: Silicidation techniques with improved rare earth silicide morphology for fabrication of semiconductor device contacts. For example, a method for forming silicide includes implanting a silicon layer with an amorphizing species to fond an amorphous silicon region in the silicon layer and depositing a rare earth metal film on the silicon layer in contact with the amorphous silicon region. A silicide process is then performed to combine the rare earth metal film and the amorphous silicon region to form a silicide film on the silicon layer.Type: ApplicationFiled: August 30, 2012Publication date: February 28, 2013Applicant: International Business Machines CorporationInventors: Paul R. Besser, Roy A. Carruthers, Christopher P. D'Emic, Christian Lavoie, Conal E. Murray, Kazuya Ohuchi, Christopher Scerbo, Bin Yang
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Publication number: 20130049199Abstract: Silicidation techniques with improved rare earth silicide morphology for fabrication of semiconductor device contacts. For example, a method for forming silicide includes implanting a silicon layer with an amorphizing species to form an amorphous silicon region in the silicon layer and depositing a rare earth metal film on the silicon layer in contact with the amorphous silicon region. A suicide process is then performed to combine the rare earth metal film and the amorphous silicon region to form a silicide film on the silicon layer.Type: ApplicationFiled: August 31, 2011Publication date: February 28, 2013Applicant: International Business Machines CorporationInventors: Paul R. Besser, Roy A. Carruthers, Christopher P. D'Emic, Christian Lavoie, Conal E. Murray, Kazuya Ohuchi, Christopher Scerbo, Bin Yang
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Patent number: 8153514Abstract: The present invention provides a gate stack structure that has high mobilities and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800° C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8×1010 charges/cm2 or less, a peak mobility of about 250 cm2V-s or greater and substantially no mobility degradation at about 6.0×1012 inversion charges/cm2 or greater.Type: GrantFiled: August 7, 2008Date of Patent: April 10, 2012Assignee: International Business Machines CorporationInventors: Wanda Andreoni, Alessandro C. Callegari, Eduard A. Cartier, Alessandro Curioni, Christopher P. D'Emic, Evgeni Gousev, Michael A. Gribelyuk, Paul C. Jamison, Rajarao Jammy, Dianne L. Lacey, Fenton R. McFeely, Vijay Narayanan, Carlo A. Pignedoli, Joseph F. Shepard, Jr., Sufi Zafar
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Publication number: 20080293259Abstract: The present invention provides a gate stack structure that has high mobilities and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800° C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8×1010 charges/cm2 or less, a peak mobility of about 250 cm2V-s or greater and substantially no mobility degradation at about 6.0×1012 inversion charges/cm2 or greater.Type: ApplicationFiled: August 7, 2008Publication date: November 27, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Wanda Andreoni, Alessandro C. Callegari, Eduard A. Cartier, Alessandro Curioni, Christopher P. D'Emic, Evgeni Gousev, Michael A. Gribelyuk, Paul C. Jamison, Rajarao Jammy, Dianne L. Lacey, Fenton R. McFeely, Vijay Narayanan, Carlo A. Pignedoli, Joseph F. Shepard, JR., Sufi Zafar
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Publication number: 20080017936Abstract: A semiconductor structure, particularly a gate stack, useful in field effect transistors (FETs) in which the threshold voltage thereof is controlled by introducing a fixed spatial distribution of electric charge density to the gate dielectric material and a method of forming the same are provided. nFETs and/or pFETs structures are disclosed. In accordance with the present invention, the fixed spatial distribution of electric charge density of the gate stack or FET denotes an electrical charge density that occupies space which remains substantially constant as a function of time under device operation conditions and is non-zero at least at one location within the dielectric material or at its interface with the channel, gate electrode, spacer, or any other structural elements of the device.Type: ApplicationFiled: June 29, 2006Publication date: January 24, 2008Applicant: International Business Machines CorporationInventors: Douglas A. Buchanan, Eduard A. Cartier, Kevin K. Chan, Leland Chang, Christopher P. D'Emic, Martin M. Frank, Evgeni Gusev, Jin-Ping Han, Rajarao Jammy, Vamsi K. Paruchuri, Sufi Zafar
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Patent number: 7115959Abstract: The present invention provides a gate stack structure that has high mobilites and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800° C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8×1010 charges/cm2 or less, a peak mobility of about 250 cm2/V-s or greater and substantially no mobility degradation at about 6.0×1012 inversion charges/cm2 or greater.Type: GrantFiled: June 22, 2004Date of Patent: October 3, 2006Assignee: International Business Machines CorporationInventors: Wanda Andreoni, Alessandro C. Callegari, Eduard A. Cartier, Alessandro Curioni, Christopher P. D'Emic, Evengi Gousev, Michael A. Gribelyuk, Paul C. Jamison, Rajarao Jammy, Dianne L. Lacey, Fenton R. McFeely, Vijay Narayanan, Carlo A. Pignedoli, Joseph P. Shepard, Jr., Sufi Zafar
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Patent number: 7109559Abstract: A method for forming a gate dielectric for an integrated circuit device. In an exemplary embodiment of the invention, the method includes forming an initial oxynitride layer upon a substrate material, the oxynitride layer having an initial physical thickness. The initial oxynitride layer is then subjected to a plasma nitridation, the plasma nitridation resulting in final oxynitride layer having a final physical thickness.Type: GrantFiled: November 5, 2004Date of Patent: September 19, 2006Assignee: International Business Machines CorporationInventors: Mukesh V. Khare, Christopher P. D'Emic, Thomas T. Hwang, Paul C. Jamison, James J. Quinlivan, Beth A. Ward
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Patent number: 7078300Abstract: A method for producing thin, below 6 nm of equivalent oxide thickness, germanium oxynitride layer on Ge-based materials for use as gate dielectric is disclosed. The method involves a two step process. First, nitrogen is incorporated in a surface layer of the Ge-based material. Second, the nitrogen incorporation is followed by an oxidation step. The method yields excellent thickness control of high quality gate dielectrics for Ge-based field effect devices, such as MOS transistors. Structures of devices having the thin germanium oxynitride gate dielectric and processors made with such devices are disclosed, as well.Type: GrantFiled: September 27, 2003Date of Patent: July 18, 2006Assignee: International Business Machines CorporationInventors: Evgeni Gousev, Huiling Shang, Christopher P. D'Emic, Paul M. Kozlowski
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Patent number: 6893979Abstract: A method for forming a gate dielectric for an integrated circuit device. In an exemplary embodiment of the invention, the method includes forming an initial oxynitride layer upon a substrate material, the oxynitride layer having an initial physical thickness. The initial oxynitride layer is then subjected to a plasma nitridation, the plasma nitridation resulting in final oxynitride layer having a final physical thickness.Type: GrantFiled: March 15, 2001Date of Patent: May 17, 2005Assignee: International Business Machines CorporationInventors: Mukesh V. Khare, Christopher P. D'Emic, Thomas T. Hwang, Paul C. Jamison, James J. Quinlivan, Beth A. Ward
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Patent number: 6770500Abstract: A process of passivating a metal-gated CMOS structure in which a metal-gated CMOS structure is passivated in an atmosphere of molecular hydrogen at a temperature of between about 250° C. and about 500° C. and a pressure of at least about 200 Torr. The present process provides a lower interface state density than obtainable by prior art passivation processes.Type: GrantFiled: March 15, 2002Date of Patent: August 3, 2004Assignee: International Business Machines CorporationInventors: Alessandro Cesare Callegari, Christopher P. D'emic, Hyungjun Kim, Fenton Read McFeely, Vijay Narayanan, John Jacob Yurkas