Abstract: A method for forming an ultra thin gate dielectric for an integrated circuit device is disclosed. In an exemplary embodiment of the invention, the method includes forming an initial nitride layer upon a substrate by rapidly heating the substrate in the presence of an ammonia (NH3) gas, and then re-oxidizing the initial nitride layer by rapidly heating the initial nitride layer in the presence of a nitric oxide (NO) gas, thereby forming an oxynitride layer. The oxynitride layer has a nitrogen concentration therein of at about 1.0×1015 atoms/cm2 to about 6.0×1015 atoms/cm2, and has a thickness which may be controlled within a sub 10 Å range.

Abstract: A process of passivating a metal-gated CMOS structure in which a metal-gated CMOS structure is passivated in an atmosphere of molecular hydrogen at a temperature of between about 250° C. and about 500° C. and a pressure of at least about 200 Torr. The present process provides a lower interface state density than obtainable by prior art passivation processes.

Abstract: A method for forming strained Si or SiGe on relaxed SiGe on insulator (SGOI) is described incorporating growing epitaxial Si1−yGey layers on a semiconductor substrate, implanting hydrogen into a selected Si1−yGey layer to form a hydrogen-rich defective layer, smoothing surfaces by Chemo-Mechanical Polishing, bonding two substrates together via thermal treatments and separating two substrates at the hydrogen-rich defective layer. The separated substrates may have its upper surface smoothed by CMP for epitaxial deposition of relaxed Si1−yGey, and strained Si1−yGey depending upon composition, strained Si, strained SiC, strained Ge, strained GeC, and strained Si1−yGeyC.

Abstract: A method for forming an ultra thin gate dielectric for an integrated circuit device is disclosed. In an exemplary embodiment of the invention, the method includes forming an initial nitride layer upon a substrate by rapidly heating the substrate in the presence of an ammonia (NH3) gas, and then re-oxidizing the initial nitride layer by rapidly heating the initial nitride layer in the presence of a nitric oxide (NO) gas, thereby forming an oxynitride layer. The oxynitride layer has a nitrogen concentration therein of at about 1.0×1015 atoms/cm2 to about 6.0×1015 atoms/cm2, and has a thickness which may be controlled within a sub 10 Å range.

Abstract: A method for forming a gate dielectric for an integrated circuit device. In an exemplary embodiment of the invention, the method includes forming an initial oxynitride layer upon a substrate material, the oxynitride layer having an initial physical thickness. The initial oxynitride layer is then subjected to a plasma nitridation, the plasma nitridation resulting in final oxynitride layer having a final physical thickness.

Abstract: A method for integrating a high-k material into CMOS processing schemes is provided. The method includes forming an interfacial oxide, oxynitride and/or nitride layer on a device region of a semiconductor substrate, said interfacial layer having a thickness of less than 10 Å; and (b) forming a high-k dielectric material on said interfacial oxide, oxynitride and/or, nitride layer, said high-k dielectric having a dielectric constant, k, of greater than 8.

Abstract: A cluster system controls the interface properties of the films that deposit or grow on a silicon substrate. The system comprises a plurality of horizontal quartz chamber or tubes each of which can hold a large quantity of wafers, a transfer chamber and a load/unload chamber. Several process steps can be executed sequentially in different tubes without intermediate exposure to ambient air. A transfer chamber connects them and allows wafer transportation from one tube to another in an absolute controlled UHV environment which limits any contamination such as H2O, to less than a monolayer level. In addition, each tube can be pumped down to UHV pressure regime to avoid further cross contamination between tubes or particle generation. Since some of the process requires elevated temperature, all wafers are placed vertically on the quartz boat to prevent any wafer sagging as in a vertical furnace.