Abstract: The present disclosure relates to embodiments of bus interface systems capable of dealing with the tougher half clock cycle of SREAD commands in the new mobile industry processor interface (MIPI) radio frequency front end (RFFE) version 2.0 standard. With regard to the slave bus controllers of the bus interface systems disclosed herein, the slave bus controller is configured to operate the slave bus driver such that the data bus line is driven towards a minimum voltage level in response to a final clock edge of the clock signal during the bus park subframe. To ensure compliance with the MIPI RFFE version 2.0 standard, the slave bus controller is configured to detect when the data bus line has been driven within a first voltage range after the final clock edge and continue driving the data bus line 16 even after the bus park half clock period is finished.

Abstract: A programmable slave circuit on a communication bus is provided. In a non-limiting example, the communication bus can be a radio frequency front-end (RFFE) bus operating based on a master-slave topology and the programmable slave circuit can be an RFFE slave circuit on the RFFE bus. The programmable slave circuit is configured to receive a high-level command(s) (e.g., a macro word) over the communication bus. A processing circuit in the programmable slave circuit is programmed to generate a low-level command(s) (e.g., a bitmap word) for controlling a coupled circuit(s) based on the high-level command(s). In this regard, it is possible to program or reprogram the processing circuit, for example via over-the-air (OTA) updates, based on the high-level command(s) to be supported, thus making it possible to flexibly customize the programmable slave circuit according to operating requirements and configurations.

Abstract: A single-wire peer-to-peer (P2P) bus apparatus is provided. The single-wire P2P bus apparatus includes a first peer device and a second peer device(s) coupled to a single-wire bus that correspond to a first bus access priority and a second bus access priority(s), respectively. Any of the first peer device and the second peer device(s) can contend for access to the single-wire bus by asserting a bus contention indication(s) when the single-wire bus is in a defined bus state. A winner for the single-wire bus may be a peer device having a highest bus access priority among those peer devices asserting the bus contention indication(s). In this regard, any peer device on the single-wire bus can have a chance to initiate communications over the single-wire bus, thus making it possible for the single-wire bus to function based on bidirectional P2P bus architecture capable of supporting more application and/or deployment scenarios.

Abstract: An envelope tracking (ET) amplifier apparatus is provided. The ET amplifier apparatus includes an ET integrated circuit (ETIC) and a distributed ETIC (DETIC) coupled to a single-wire bus that correspond to a first bus access priority and a second bus access priority, respectively. The ETIC and the DETIC can contend for access to the single-wire bus by asserting a bus contention indication(s) when the single-wire bus is in a defined bus state configured to permit bus contention. In a non-limiting example, a winner for the single-wire bus is a peer device having a highest bus access priority between the ETIC and the DETIC. In this regard, each of the ETIC and the DETIC can have a chance to initiate communications over the single-wire bus, thus making it possible for the single-wire bus to function based on bidirectional peer-to-peer (P2P) bus architecture capable of supporting more application and/or deployment scenarios.

Abstract: A single-wire bus (SuBUS) apparatus is provided. The SuBUS apparatus includes a master circuit coupled to a slave circuit(s) by a SuBUS. The master circuit can enable or suspend a SuBUS telegram communication over the SuBUS. When the master circuit suspends the SuBUS telegram communication over the SuBUS, the slave circuit(s) may draw a charging current via the SuBUS to perform a defined slave operation. Notably, the master circuit may not have knowledge about exact completion time of the defined slave operation and thus may be unable to resume the SuBUS telegram communication in a timely manner. The slave circuit(s) can be configured to generate a predefined interruption pulse sequence to cause the master circuit to resume the SuBUS telegram communication over the SuBUS. As such, it may be possible for the master circuit to quickly resume the SuBUS telegram communication, thus helping to improve throughput of the SuBUS.

Abstract: A hybrid bus apparatus is provided. The hybrid bus apparatus includes a hybrid bus bridge circuit configured to couple a master(s) with one or more auxiliary slaves via heterogeneous communication buses. The hybrid bus bridge circuit and the auxiliary slaves are associated with respective unique slave identifications (USIDs). The master(s) can only support a fixed number of the USIDs, and thus a fixed number of the auxiliary slaves. The hybrid bus bridge circuit is configured to opportunistically mask some or all of the auxiliary slaves such that the respective USIDs associated with the masked auxiliary slaves can be reused by the master(s) to support additional slaves. As such, it may be possible to extend the capability of the master(s) to support more slaves than the fixed number of USIDs the master(s) can provide, thus enabling flexible heterogeneous bus deployment in an electronic device incorporating the hybrid bus apparatus.

Abstract: A single-wire bus (SuBUS) slave circuit is provided. The SuBUS slave circuit is coupled to a SuBUS bridge circuit via a SuBUS and can be configured to perform a slave task that may block communication on the SuBUS. Notably, the SuBUS slave circuit may not be equipped with an accurate timing reference source that can determine a precise timing for terminating the slave task and unblock the SuBUS. Instead, the SuBUS slave circuit is configured to terminate the slave task and unblock the SuBUS based on a self-determined slave free-running-oscillator count derived from a start-of-sequence training sequence that precedes any SuBUS telegram of a predefined SuBUS operation, even though the SuBUS operation is totally unrelated to the slave task. As such, it may be possible to eliminate the accurate timing reference source from the SuBUS slave circuit, thus helping to reduce cost and current drain in the SuBUS slave circuit.

Abstract: A radio frequency front-end (RFFE) bus hub circuit and related apparatus are provided. In examples discussed herein, the RFFE bus hub circuit can be configured to bridge an RFFE bus with a number of auxiliary RFFE buses. In a non-limiting example, each of the auxiliary RFFE buses can be configured to support up to fourteen RFFE slaves. Thus, by bridging the RFFE bus with multiple auxiliary RFFE buses using the RFFE bus hub circuit, it may be possible to support more than fifteen RFFE slaves without adding an additional RFFE bus. As a result, it may be possible to reduce pin count requirement for an RFFE master and/or enable flexible RFFE bus deployment in an RFFE apparatus.

Abstract: This disclosure relates generally to bus interface systems for mobile user devices. In one embodiment, the bus interface system includes a first bus interface subsystem that operates in accordance with a one wire bus protocol, a second bus interface subsystem that operates in accordance with a Mobile Industry Processor Interface (MIPI) radio frequency front end (RFFE) bus protocol, and a translation bus controller that translates commands between the first bus interface subsystem and the second bus interface system. The translation bus controller is configured to implement cross over bus operations between a master bus controller that operates in accordance with in the one wire bus protocol and a slave bus controller in the second bus interface system. In this manner, the translation bus allows the master bus controller to be the master of different bus systems that operate in accordance with different bus protocols.

Abstract: An electrical current measurement circuit is provided. The electrical current measurement circuit is configured to receive a sense current proportionally related to an electrical current of interest to continuously charge a capacitor to a sense voltage. The electrical current measurement circuit is configured to determine whether the sense voltage reaches a predefined voltage threshold and reduce the sense voltage to below the predefined voltage threshold in response to the sense voltage reaching the predefined voltage threshold. The electrical current measurement circuit counts each occurrence of the sense voltage reaching the predefined voltage threshold and quantifies the electrical current based on a total count of the sense voltage reaching the predefined voltage threshold during the predefined measurement period.

Abstract: A hybrid bus hub circuit and related apparatus are provided. The bus hub circuit can be configured to bridge a radio frequency front-end (RFFE) bus with a number of auxiliary buses of different types. Each of the auxiliary buses may support a fixed number of slaves identified respectively by a unique slave identification (USID). The hybrid bus hub circuit can be configured to selectively activate an auxiliary bus(es) for communication with the RFFE bus, thus making it possible to reuse a same set of USIDs among the auxiliary buses without causing potential identification conflict. As such, it may be possible to support more slaves in an apparatus with a single RFFE bus. As a result, it may be possible to reduce pin count requirement for an RFFE master and/or enable flexible heterogeneous bus deployment in the apparatus.

Abstract: A radio frequency front-end (RFFE) bus hub circuit and related apparatus are provided. In examples discussed herein, the RFFE bus hub circuit can be configured to bridge an RFFE bus with a number of auxiliary RFFE buses. In a non-limiting example, each of the auxiliary RFFE buses can be configured to support up to fourteen RFFE slaves. Thus, by bridging the RFFE bus with multiple auxiliary RFFE buses using the RFFE bus hub circuit, it may be possible to support more than fifteen RFFE slaves without adding an additional RFFE bus. As a result, it may be possible to reduce pin count requirement for an RFFE master and/or enable flexible RFFE bus deployment in an RFFE apparatus.

Abstract: A heterogeneous bus bridge circuit and related apparatus are provided. The heterogeneous bus bridge circuit is configured to bridge a radio frequency front-end (RFFE) bus with a number of auxiliary buses that are different from the RFFE bus. Each of the auxiliary buses may support a fixed number of slaves identified respectively by a unique slave identification (USID). In examples discussed herein, the heterogeneous bus bridge circuit can be configured to selectively activate an auxiliary bus for communication with the RFFE bus, thus making it possible to reuse a same set of USIDs among the auxiliary buses without causing potential identification conflict. As such, it may be possible to support more slaves in an apparatus with a single RFFE bus. As a result, it may be possible to reduce pin count requirement for an RFFE master and/or enable flexible heterogeneous bus deployment in the apparatus.

Abstract: Embodiments of a bus interface system are disclosed. The bus interface system includes a master bus controller and a slave bus controller coupled to a bus line. The master bus controller and the slave bus controller are configured to perform read operations using error codes and error checks. For example, the error codes may be cyclic redundancy codes (CRC). In this manner, accuracy is ensured during communications between the slave bus controller and the master bus controller.

Abstract: A single-wire bus (SuBUS) slave circuit is provided. The SuBUS slave circuit is coupled to a SuBUS bridge circuit via a SuBUS and can be configured to perform a slave task that may block communication on the SuBUS. Notably, the SuBUS slave circuit may not be equipped with an accurate timing reference source that can determine a precise timing for terminating the slave task and unblock the SuBUS. Instead, the SuBUS slave circuit is configured to terminate the slave task and unblock the SuBUS based on a self-determined slave free-running-oscillator count derived from a start-of-sequence training sequence that precedes any SuBUS telegram of a predefined SuBUS operation, even though the SuBUS operation is totally unrelated to the slave task. As such, it may be possible to eliminate the accurate timing reference source from the SuBUS slave circuit, thus helping to reduce cost and current drain in the SuBUS slave circuit.

Abstract: This disclosure relates generally to digital bus interfaces. In one embodiment, a bus interface system includes a master bus controller and a slave bus controller coupled along a bus line. The master bus controller is configured to generate an input data signal that is received by the slave bus controller along the bus line. The slave bus controller includes power conversion circuitry that includes a power converter configured to convert the input data signal from the master bus controller into a supply voltage. The power conversion circuitry is also configured to generate a charge current from the input data signal. In this manner, the charge current can be used to regulate the supply voltage and maintain the appropriate charge.

Abstract: The disclosure relates to bus interface systems. In one embodiment, the bus interface system includes a bus line along with a master bus controller and a slave bus controller coupled to the bus line. In order to start a data frame, the master bus controller is configured to generate a sequence of data pulses along the bus line such that the sequence of data pulses is provided in accordance to a start of sequence (SOS) pulse pattern. The slave bus controller is configured to recognize that the sequence of data transmitted along the bus line by the master bus controller has been provided in accordance with the SOS pulse pattern. In this manner, the slave bus controller can detect when the master bus controller has started a new data frame. As such, the exchange of information through data frames can be synchronized along the bus line with requiring an additional bus line for a clock signal.

Abstract: The present disclosure relates to a bus interface system including a bus line, master integrated circuitry (IC), and slave IC. The master IC is coupled to the bus line and configured to transmit the data signal to the slave IC through the bus line. The slave IC is coupled to the bus line so as to receive the data signal from the master IC and includes a supply capacitor, which is configured to store power from the data signal and provide a supply voltage to the slave IC. When the bus line is in the low state, the supply capacitor is isolated from the bus line. When the bus line is in the high state, the supply capacitor is allowed to extract power from the data signal on the bus line.

Abstract: A digital current sensing circuit and related apparatus is provided. In one aspect, a digital current sensing circuit can be configured to estimate a battery current in a coupled circuit based on a voltage corresponding to the battery current. More specifically, the digital current sensing circuit generates an analog sense current proportional to the battery current based on the voltage and digitally processes the analog sense current to generate a battery current indication signal indicative of an estimation of the battery current. In another aspect, a number of digital current sensing circuits can be provided in an apparatus to concurrently estimate a number of battery currents in a number of circuits (e.g., charge pump circuits). As a result, it may be possible to test, debug, and/or fine-tune the apparatus based on the estimated battery currents for improved performance.

Abstract: Embodiments of a bus interface system are disclosed. In one embodiment, the bus interface system includes a master bus controller and a slave bus controller coupled to a bus line. The master bus controller is configured to generate a first set of data pulses along the bus line representing a payload segment. The slave bus controller is configured to decode the first set of data pulses representing the payload segment into a decoded payload segment. The slave bus controller is then configured to perform a first error check on the decoded payload segment. Furthermore, the slave bus controller is configured to generate an acknowledgment signal along the bus line so that the acknowledgement signal indicates that the decoded payload segment passed the first error check. In this manner, the master bus controller can determine that the slave bus controller received an accurate copy of the payload segment.