Abstract: A device includes a memory, at least two input/output (IO) pins, and slave identifier (ID) selection circuitry. The memory stores a slave ID, which identifies the device to other devices in a serial communication process. The slave ID selection circuitry changes the stored slave ID based on which one of the IO pins is coupled to a supply voltage. By changing the slave ID of the device based on which one of the IO pins is coupled to a supply voltage, a number of devices with otherwise identical slave IDs may change their slave IDs in order to participate in a serial communication process on the same bus. Further, the slave ID of the device may be changed without using an additional IO pin on the device.

Abstract: Disclosed is a digital communication control system having a serial bus buffer that includes a primary interface adapted to support serial communication over a primary bus, a buffered interface adapted to support serial communication over a buffered bus, and a controller coupled between the primary bus and the buffered bus. The primary bus is coupled to a first device and at least one second device and the buffered bus is coupled to at least one third device. The controller is adapted to receive a first data signal and a clock signal at the primary interface and replicate the first data signal and the clock signal at the buffered interface.

Abstract: An architecture for a radio frequency (RF) front-end is disclosed. The architecture for the RF front-end includes a circuit module that includes a plurality of dies partitioned on the circuit module. A plurality of filter banks with individual ones of the plurality of filter banks disposed on each of the plurality of circuit dies is also included. Further included is a plurality of switches having individual ones of the plurality of switches coupled to corresponding ones of the plurality of filter banks and in at least one embodiment a control system is configured to open and close selected ones of the plurality of switches.

Abstract: This disclosure relates generally to radio frequency (RF) switching converters and RF amplification devices that use RF switching converters. For example, an RF switching converter may include a switching circuit that receives a power source voltage and a switching controller that receives a target average frequency value identifying a target average frequency. The switching circuit is switchable so as to generate a pulsed output voltage from the power source voltage. The switching controller switches the switching circuit such that the pulsed output voltage has an average pulse frequency. The switching controller also detects that the average pulse frequency of the pulsed output voltage during a time period differs from the target average frequency, and reduces a difference between the average pulse frequency and the target average frequency. In this manner, the effects of manufacturing variations and operational variations on the average pulse frequency can be eliminated, or at least diminished.

Abstract: A power management system, which includes a parallel amplifier circuit and a switch mode power supply converter, is disclosed. The switch mode power supply converter cooperatively operates with the parallel amplifier circuit to form the power management system. The power management system operates in one of a high power modulation mode, a medium power modulation mode, and a low power average power tracking mode. Further, during the high power modulation mode and the medium power modulation mode, the power management system controls a power amplifier supply voltage to a radio frequency power amplifier to provide envelope tracking. During the low power average power tracking mode, the power management system controls the power amplifier supply voltage to the radio frequency power amplifier to provide average power tracking.

Abstract: A direct current (DC)-DC converter, which includes an open loop ripple cancellation circuit, a switching supply, and a parallel amplifier, is disclosed. During a calibration mode, the parallel amplifier provides a parallel amplifier output current to regulate a power supply output voltage based on a calibration setpoint. The switching supply drives the parallel amplifier output current toward zero using a switching control signal, such that during the calibration mode, an estimate of a current gain is based on the switching control signal. Further, during the calibration mode, the open loop ripple cancellation circuit is disabled. During a normal operation mode, the open loop ripple cancellation circuit provides a ripple cancellation current, which is based on the estimate of the current gain.

Abstract: The disclosure relates to bus interface systems. In one embodiment, the bus interface system includes a bus line along with a master bus controller and a slave bus controller coupled to the bus line. In order to start a data frame, the master bus controller is configured to generate a sequence of data pulses along the bus line such that the sequence of data pulses is provided in accordance to a start of sequence (SOS) pulse pattern. The slave bus controller is configured to recognize that the sequence of data transmitted along the bus line by the master bus controller has been provided in accordance with the SOS pulse pattern. In this manner, the slave bus controller can detect when the master bus controller has started a new data frame. As such, the exchange of information through data frames can be synchronized along the bus line with requiring an additional bus line for a clock signal.

Abstract: Embodiments of a bus interface system are disclosed. The bus interface system includes a master bus controller and a slave bus controller coupled to a bus line. The master bus controller and the slave bus controller are configured to perform read operations using error codes and error checks. For example, the error codes may be cyclic redundancy codes (CRC). In this manner, accuracy is ensured during communications between the slave bus controller and the master bus controller.

Abstract: Embodiments of bus interface systems are disclosed. In one embodiment, a bus interface system includes a master bus controller and a slave bus controller coupled along a bus line. The master bus controller is configured to generate an input data signal that is received by the slave bus controller along the bus line. The slave bus controller includes power conversion circuitry configured to convert the input data signal from the master bus controller into a supply voltage. By providing the power conversion circuitry, the slave bus controller is powered using the input data signal and without requiring an additional bus line to transfer a supply voltage to the slave bus controller.

Abstract: Embodiments of bus interface systems and methods of operating the same are disclosed. In one embodiment, a bus interface system includes a master bus controller and multiple slave bus controllers that are each coupled to a bus line. The master bus controller is configured to generate a first set of data pulses along the bus line representing a payload segment. Each of the slave bus controllers decodes the first set of data pulses along the bus line representing the payload segment and performs an error check. Each slave bus controller is then configured to generate an acknowledgement pulse along the bus line to indicate that the slave bus controller's particular error check was passed. In this manner, the bus interface system can perform a group write bus function and the master bus controller can determine that the multiple slave bus controllers each received an accurate copy of the payload segment.

Abstract: Embodiments of a bus interface system are disclosed. In one embodiment, the bus interface system includes a master bus controller and a slave bus controller coupled to a bus line. The master bus controller is configured to generate a first set of data pulses along the bus line representing a payload segment. The slave bus controller is configured to decode the first set of data pulses representing the payload segment into a decoded payload segment. The slave bus controller is then configured to perform a first error check on the decoded payload segment. Furthermore, the slave bus controller is configured to generate an acknowledgment signal along the bus line so that the acknowledgement signal indicates that the decoded payload segment passed the first error check. In this manner, the master bus controller can determine that the slave bus controller received an accurate copy of the payload segment.

Abstract: A bus interface system is disclosed that includes a master bus controller and a slave bus controller that are coupled by a bus line. The slave bus controller includes a decoder that allows for data to be transmitted along just the bus line. The decoder includes an oscillator, a first counter, and a comparison circuit. The oscillator is configured to be enabled by data pulses defined by the input data signal and generate oscillation pulses while enabled. The first counts the oscillation pulses and indicates a number of the oscillation pulses generated during a time slot. The comparison circuit is configured to this number with a reference number and generate a data output that represents a first logical value in response to the number being greater than the reference parameter and represents a second logical value in response to the number being less than the reference parameter.

Abstract: Two Manchester encoded bit streams each bit stream with accompanying embedded clock data are disclosed. The two encoded bit streams are encoded at the source using opposite polarities of the source clock to position transitions within the bit streams at the rising and falling edges of the source clock. The receiver may extract the clock data from both bit streams. Because both rising and falling edge clock data is available between the two bit streams, the receiver does not need a phase locked loop (PLL) or incur the accompanying expense of such PLL. Further, by avoiding use of a PLL, a nearly all digital circuit may be created, which may provide further cost and space savings. Still further, a higher data throughput is provided without increasing pin count or signal bandwidth.

Abstract: A device includes a memory, at least two input/output (IO) pins, and slave identifier (ID) selection circuitry. The memory stores a slave ID, which identifies the device to other devices in a serial communication process. The slave ID selection circuitry changes the stored slave ID based on which one of the IO pins is coupled to a supply voltage. By changing the slave ID of the device based on which one of the IO pins is coupled to a supply voltage, a number of devices with otherwise identical slave IDs may change their slave IDs in order to participate in a serial communication process on the same bus. Further, the slave ID of the device may be changed without using an additional IO pin on the device.

Abstract: A configurable 2-wire/3-wire serial communications interface (C23SCI), which includes start-of-sequence (SOS) detection circuitry and sequence processing circuitry, is disclosed. When the SOS detection circuitry is coupled to a 2-wire serial communications bus, the SOS detection circuitry detects an SOS of a received sequence based on a serial data signal and a serial clock signal. When the SOS detection circuitry is coupled to a 3-wire serial communications bus, the SOS detection circuitry detects the SOS of the received sequence based on a chip select (CS) signal. In response to detecting the SOS, the SOS detection circuitry provides an SOS detection signal to the sequence processing circuitry, which initiates processing of the received sequence using the serial data signal and the serial clock signal. The received sequence is associated with one of multiple serial communications protocols.

Abstract: An automatically configurable 2-wire/3-wire serial communications interface (AC23SCI), which includes start-of-sequence (SOS) detection circuitry and sequence processing circuitry, is disclosed. When the SOS detection circuitry is coupled to a 2-wire serial communications bus, the SOS detection circuitry detects an SOS of a received sequence based on a serial data signal and a serial clock signal. When the SOS detection circuitry is coupled to a 3-wire serial communications bus, the SOS detection circuitry detects the SOS of the received sequence based on a chip select (CS) signal. The SOS detection circuitry provides an indication of detection of the SOS to the sequence processing circuitry, which initiates processing of the received sequence using the serial data signal and the serial clock signal upon the detection of the SOS. As such, the AC23SCI automatically configures itself for operation with some 2-wire and some 3-wire serial communications buses without external intervention.

Abstract: Two Manchester encoded bit streams each bit stream with accompanying embedded clock data are disclosed. The two encoded bit streams are encoded at the source using opposite polarities of the source clock to position transitions within the bit streams at the rising and falling edges of the source clock. The receiver may extract the clock data from both bit streams. Because both rising and falling edge clock data is available between the two bit streams, the receiver does not need a phase locked loop (PLL) or incur the accompanying expense of such PLL. Further, by avoiding use of a PLL, a nearly all digital circuit may be created, which may provide further cost and space savings. Still further, a higher data throughput is provided without increasing pin count or signal bandwidth.

Abstract: A protection system and method for protecting a direct current to direct current voltage converter (DC-DC converter) from a potentially damaging excessive output current due to exposure to a relatively strong magnetic field is disclosed. The system includes a detector circuit configured to monitor a signal characteristic of the DC-DC converter, and a linear regulator having an output coupled to the load output of the DC-DC converter. The system further includes a control system configured to disable a load output of the DC-DC converter and enable the output of the linear regulator when the detector detects that the signal characteristic has moved outside a predetermined threshold range. Moreover, the control system is further configured to disable the output of the linear regulator after a predetermined time period, and enable the load output of the DC-DC converter after the predetermined time period.

Abstract: Disclosed is a digital communication control system having a serial bus buffer that includes a primary interface adapted to support serial communication over a primary bus, a buffered interface adapted to support serial communication over a buffered bus, and a controller coupled between the primary bus and the buffered bus. The primary bus is coupled to a first device and at least one second device and the buffered bus is coupled to at least one third device. The controller is adapted to receive a first data signal and a clock signal at the primary interface and replicate the first data signal and the clock signal at the buffered interface.

Abstract: The present disclosure relates to RF front-end (RFFE) circuitry that includes multiple RFFE circuits, each of which may be provided by a separate integrated circuit (IC), front-end module, or both. As such, the RFFE circuits may be connected to one another using an RFFE serial communications bus. Further, one or more of the RFFE circuits may need an accurate clock source for analog-to-digital conversion (ADC), digital-to-analog conversion (DAC), calibration, sensor measurements, or the like. Instead of including an integral clock source circuit or receiving a separate external clock signal, an RFFE circuit may extract clock information from the RFFE serial communications bus to provide one or more clock signals. The clock information may be associated with one or more serial communications commands via the RFFE serial communications bus, may be associated with alternate functionality of the RFFE serial communications bus, or both.