Patents by Inventor Christopher W. Steffen
Christopher W. Steffen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11714127Abstract: On-chip spread spectrum characterization including obtaining, from a skitter circuit, skitter data comprising a spread width corresponding to an amplitude of a spread of a spread spectrum clock signal; setting an offset pointer to a center of the spread width corresponding to the amplitude of the spread; retrieving, for each of a number of reference clock cycles, edge data indicating a location, within the spread width, of an edge of the spread spectrum during the reference clock cycle; incrementing, using the edge data, an offset counter for each reference clock cycle during which the edge of the spread spectrum crosses the offset pointer; and calculating a frequency of the spread spectrum using the offset counter and the number of reference clock cycles.Type: GrantFiled: June 12, 2018Date of Patent: August 1, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christopher W. Steffen, John P. Borkenhagen
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Patent number: 11092763Abstract: A method of forming a coaxial wire that includes providing a sacrificial trace structure using an additive forming method, the sacrificial trace structure having a geometry for the coaxial wire, and forming a continuous seed metal layer on the sacrificial trace structure. The sacrificial trace structure may be removed and a first interconnect metal layer may be formed on the continuous seed layer. An electrically insulative layer may then be formed on the first interconnect metal layer, and a second interconnect metal layer is formed on the electrically insulative layer. Thereafter, a dielectric material is formed on the second interconnect metal layer to encapsulate a majority of an assembly of the first interconnect metal layer, electrically insulative layer and second interconnect metal layer that provides said coaxial wire. Ends of the coaxial wire may be exposed through opposing surfaces of the dielectric material to provide that the coaxial wire extends through that dielectric material.Type: GrantFiled: August 1, 2018Date of Patent: August 17, 2021Assignee: International Business Machines CorporationInventors: Daniel J. Buvid, Eric J. Campbell, Sarah K. Czaplewski, Christopher W. Steffen
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Patent number: 11016255Abstract: A method of forming a coaxial wire that includes providing a sacrificial trace structure using an additive forming method, the sacrificial trace structure having a geometry for the coaxial wire, and forming a continuous seed metal layer on the sacrificial trace structure. The sacrificial trace structure may be removed and a first interconnect metal layer may be formed on the continuous seed layer. An electrically insulative layer may then be formed on the first interconnect metal layer, and a second interconnect metal layer is formed on the electrically insulative layer. Thereafter, a dielectric material is formed on the second interconnect metal layer to encapsulate a majority of an assembly of the first interconnect metal layer, electrically insulative layer and second interconnect metal layer that provides said coaxial wire. Ends of the coaxial wire may be exposed through opposing surfaces of the dielectric material to provide that the coaxial wire extends through that dielectric material.Type: GrantFiled: October 23, 2019Date of Patent: May 25, 2021Assignee: International Business Machines CorporationInventors: Daniel J. Buvid, Eric J. Campbell, Sarah K. Czaplewski, Christopher W. Steffen
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Patent number: 10927567Abstract: A lock system and method for alerting a user or other entity that a lock has been or is being tampered with is disclosed. The lock includes at least one enhanced security pin that is electrically isolated from the rest of the lock. When the lock picker attempts to pick the lock a portion of the enhanced security pin contacts either the plug or the outer casing of the lock to complete a circuit with an alert component. The completion of the circuit causes the alert component to generate an alert signal that can be observed by the user or other entity.Type: GrantFiled: January 1, 2019Date of Patent: February 23, 2021Assignee: International Business Machines CorporationInventors: Chad M. Albertson, Eric J. Campbell, Nicholas J. Ollerich, Christopher W. Steffen
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Patent number: 10833001Abstract: A method of forming an interconnect that includes providing a sacrificial trace structure using an additive forming method. The sacrificial trace structure having a geometry for the interconnect. The method continuous with forming a continuous seed metal layer on the sacrificial trace structure; and removing the sacrificial trace structure, wherein the continuous seed metal layer remains. An interconnect metal layer may be formed on the continuous seed layer. A dielectric material may then be formed on the interconnect metal layer to encapsulate a majority of the interconnect metal layer, wherein ends of the interconnect metal layer are exposed through one surface of the dielectric material to provide an interconnect extending into a dielectric material.Type: GrantFiled: February 27, 2019Date of Patent: November 10, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Daniel J. Buvid, Eric J. Campbell, Sarah K. Czaplewski, Christopher W. Steffen
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Patent number: 10796030Abstract: Detecting an attempted theft of information stored in an RFID-enabled card, including: receiving, by a theft detection module, a transaction request, the transaction request including RFID-enabled card information; determining, by the theft detection module, that the RFID-enabled card information is mock card information, wherein mock card information is provided to an RFID reader by an RFID tag exterior to an RFID shield of an RFID-enabled card security enclosure responsive to an RFID request directed at the security enclosure; and responsive to determining that the RFID-enabled card information is mock card information, initiating, by the theft detection module, one or more security actions.Type: GrantFiled: October 27, 2016Date of Patent: October 6, 2020Assignee: International Business Machines CorporationInventors: Chad M. Albertson, Eric J. Campbell, Nicholas J. Ollerich, Christopher W. Steffen
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Patent number: 10791628Abstract: A method of forming an multi-chip carrier that includes providing a trace structure using an additive forming method. The method includes forming a metal layer on a trace structure to provide electrically conductive lines. A dielectric material may then be formed on the electrically conductive lines to encapsulate a majority of the electrically conductive lines. The ends of the electrically conductive lines that are exposed through the upper surface of the dielectric material provide a top processor mount location and the ends of the electrically conductive lines that are exposed through the sidewalls of the dielectric material provide a sidewall processor mount location.Type: GrantFiled: July 3, 2019Date of Patent: September 29, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chad M. Albertson, Eric J. Campbell, Nicholas J. Ollerich, Christopher W. Steffen
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Patent number: 10727176Abstract: A method of forming an interconnect that includes providing a sacrificial trace structure using an additive forming method. The sacrificial trace structure having a geometry for the interconnect. The method continuous with forming a continuous seed metal layer on the sacrificial trace structure; and removing the sacrificial trace structure, wherein the continuous seed metal layer remains. An interconnect metal layer may be formed on the continuous seed layer. A dielectric material may then be formed on the interconnect metal layer to encapsulate a majority of the interconnect metal layer, wherein ends of the interconnect metal layer are exposed through one surface of the dielectric material to provide an interconnect extending into a dielectric material.Type: GrantFiled: February 27, 2019Date of Patent: July 28, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Daniel J. Buvid, Eric J. Campbell, Sarah K. Czaplewski, Christopher W. Steffen
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Patent number: 10613283Abstract: A method of forming a coaxial wire that includes providing a sacrificial trace structure using an additive forming method, the sacrificial trace structure having a geometry for the coaxial wire, and forming a continuous seed metal layer on the sacrificial trace structure. The sacrificial trace structure may be removed and a first interconnect metal layer may be formed on the continuous seed layer. An electrically insulative layer may then be formed on the first interconnect metal layer, and a second interconnect metal layer is formed on the electrically insulative layer. Thereafter, a dielectric material is formed on the second interconnect metal layer to encapsulate a majority of an assembly of the first interconnect metal layer, electrically insulative layer and second interconnect metal layer that provides said coaxial wire. Ends of the coaxial wire may be exposed through opposing surfaces of the dielectric material to provide that the coaxial wire extends through that dielectric material.Type: GrantFiled: August 1, 2018Date of Patent: April 7, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Daniel J. Buvid, Eric J. Campbell, Sarah K. Czaplewski, Christopher W. Steffen
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Publication number: 20200057219Abstract: A method of forming a coaxial wire that includes providing a sacrificial trace structure using an additive forming method, the sacrificial trace structure having a geometry for the coaxial wire, and forming a continuous seed metal layer on the sacrificial trace structure. The sacrificial trace structure may be removed and a first interconnect metal layer may be formed on the continuous seed layer. An electrically insulative layer may then be formed on the first interconnect metal layer, and a second interconnect metal layer is formed on the electrically insulative layer. Thereafter, a dielectric material is formed on the second interconnect metal layer to encapsulate a majority of an assembly of the first interconnect metal layer, electrically insulative layer and second interconnect metal layer that provides said coaxial wire. Ends of the coaxial wire may be exposed through opposing surfaces of the dielectric material to provide that the coaxial wire extends through that dielectric material.Type: ApplicationFiled: October 23, 2019Publication date: February 20, 2020Inventors: Daniel J. Buvid, Eric J. Campbell, Sarah K. Czaplewski, Christopher W. Steffen
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Patent number: 10554347Abstract: Low latency corrupt data tagging on a cross-chip link including receiving, from the cross-chip link, a control flit comprising a virtual channel identifier for an incoming data flit; storing the virtual channel identifier in a data pipeline and a bad data indicator (BDI) pipeline; receiving, from the cross-chip link, the incoming data flit into the data pipeline; moving, based on the virtual channel identifier in the data pipeline, the data flit from the data pipeline into an entry in a virtual channel queue corresponding to the virtual channel identifier; receiving, from the cross-chip link, a BDI for the data flit into the BDI pipeline; and moving, based on the virtual channel identifier in the BDI pipeline, the BDI for the data flit from the BDI pipeline into an entry in a BDI array corresponding to the entry in the virtual channel queue storing the data flit.Type: GrantFiled: November 27, 2017Date of Patent: February 4, 2020Assignee: International Business Machines CorporationInventors: Chad M. Albertson, Eric J. Campbell, Nicholas J. Ollerich, Christopher W. Steffen, Curtis C. Wollbrink
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Publication number: 20190377026Abstract: On-chip spread spectrum characterization including obtaining, from a skitter circuit, skitter data comprising a spread width corresponding to an amplitude of a spread of a spread spectrum clock signal; setting an offset pointer to a center of the spread width corresponding to the amplitude of the spread; retrieving, for each of a number of reference clock cycles, edge data indicating a location, within the spread width, of an edge of the spread spectrum during the reference clock cycle; incrementing, using the edge data, an offset counter for each reference clock cycle during which the edge of the spread spectrum crosses the offset pointer; and calculating a frequency of the spread spectrum using the offset counter and the number of reference clock cycles.Type: ApplicationFiled: June 12, 2018Publication date: December 12, 2019Inventors: CHRISTOPHER W. STEFFEN, JOHN P. BORKENHAGEN
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Patent number: 10505553Abstract: Detecting the health of a phase-lock loop (PLL) generating a feedback clock signal based on a reference clock signal, includes providing, by a delay line, the feedback clock signal to a plurality of latches clocked by the reference clock signal; providing, based on an output of the plurality of latches, an input to a plurality of sticky latches, the input indicating whether an edge of the feedback clock signal was detected; determining, based on a number of asserted sticky latches of the plurality of sticky latches, a phase error metric; comparing the phase error metric to a threshold; and outputting, based on the comparison, an indication of a lock state.Type: GrantFiled: November 29, 2018Date of Patent: December 10, 2019Assignee: International Business Machines CorporationInventors: Christopher W. Steffen, John P. Borkenhagen
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Publication number: 20190327833Abstract: A method of forming an multi-chip carrier that includes providing a trace structure using an additive forming method. The method includes forming a metal layer on a trace structure to provide electrically conductive lines. A dielectric material may then be formed on the electrically conductive lines to encapsulate a majority of the electrically conductive lines. The ends of the electrically conductive lines that are exposed through the upper surface of the dielectric material provide a top processor mount location and the ends of the electrically conductive lines that are exposed through the sidewalls of the dielectric material provide a sidewall processor mount location.Type: ApplicationFiled: July 3, 2019Publication date: October 24, 2019Inventors: Chad M. Albertson, Eric J. Campbell, Nicholas J. Ollerich, Christopher W. Steffen
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Patent number: 10426030Abstract: A method of forming an multi-chip carrier that includes providing a trace structure using an additive forming method. The method includes forming a metal layer on a trace structure to provide electrically conductive lines. A dielectric material may then be formed on the electrically conductive lines to encapsulate a majority of the electrically conductive lines. The ends of the electrically conductive lines that are exposed through the upper surface of the dielectric material provide a top processor mount location and the ends of the electrically conductive lines that are exposed through the sidewalls of the dielectric material provide a sidewall processor mount location.Type: GrantFiled: April 21, 2017Date of Patent: September 24, 2019Assignee: International Business Machines CorporationInventors: Chad M. Albertson, Eric J. Campbell, Nicholas J. Ollerich, Christopher W. Steffen
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Patent number: 10396944Abstract: Low latency corrupt data tagging on a cross-chip link including receiving, from the cross-chip link, a control flit comprising a virtual channel identifier for an incoming data flit; storing the virtual channel identifier in a data pipeline and a bad data indicator (BDI) pipeline; receiving, from the cross-chip link, the incoming data flit into the data pipeline; moving, based on the virtual channel identifier in the data pipeline, the data flit from the data pipeline into an entry in a virtual channel queue corresponding to the virtual channel identifier; receiving, from the cross-chip link, a BDI for the data flit into the BDI pipeline; and moving, based on the virtual channel identifier in the BDI pipeline, the BDI for the data flit from the BDI pipeline into an entry in a BDI array corresponding to the entry in the virtual channel queue storing the data flit.Type: GrantFiled: September 19, 2017Date of Patent: August 27, 2019Assignee: International Business Machines CorporationInventors: Chad M. Albertson, Eric J. Campbell, Nicholas J. Ollerich, Christopher W. Steffen, Curtis C. Wollbrink
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Publication number: 20190198439Abstract: A method of forming an interconnect that includes providing a sacrificial trace structure using an additive forming method. The sacrificial trace structure having a geometry for the interconnect. The method continuous with forming a continuous seed metal layer on the sacrificial trace structure; and removing the sacrificial trace structure, wherein the continuous seed metal layer remains. An interconnect metal layer may be formed on the continuous seed layer. A dielectric material may then be formed on the interconnect metal layer to encapsulate a majority of the interconnect metal layer, wherein ends of the interconnect metal layer are exposed through one surface of the dielectric material to provide an interconnect extending into a dielectric material.Type: ApplicationFiled: February 27, 2019Publication date: June 27, 2019Inventors: Daniel J. Buvid, Eric J. Campbell, Sarah K. Czaplewski, Christopher W. Steffen
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Publication number: 20190198440Abstract: A method of forming an interconnect that includes providing a sacrificial trace structure using an additive forming method. The sacrificial trace structure having a geometry for the interconnect. The method continuous with forming a continuous seed metal layer on the sacrificial trace structure; and removing the sacrificial trace structure, wherein the continuous seed metal layer remains. An interconnect metal layer may be formed on the continuous seed layer. A dielectric material may then be formed on the interconnect metal layer to encapsulate a majority of the interconnect metal layer, wherein ends of the interconnect metal layer are exposed through one surface of the dielectric material to provide an interconnect extending into a dielectric material.Type: ApplicationFiled: February 27, 2019Publication date: June 27, 2019Inventors: Daniel J. Buvid, Eric J. Campbell, Sarah K. Czaplewski, Christopher W. Steffen
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Publication number: 20190178883Abstract: According to an embodiment, a method of producing (e.g., making) a membrane for detecting toxic shock syndrome toxins includes depositing a second antibody on a first zone of the membrane. The second antibody is reactive with an antibody complex to cause a first indication. The antibody complex includes a first antibody coupled to a TSST-1 antigen. The method also includes depositing a third antibody on a second zone of the membrane. The third antibody is reactive with a fourth antibody to cause a second indication.Type: ApplicationFiled: February 20, 2019Publication date: June 13, 2019Inventors: Daniel J. BUVID, Eric J. CAMPBELL, Sarah K. CZAPLEWSKI, Christopher W. STEFFEN
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Patent number: 10290572Abstract: A method of forming an interconnect that includes providing a sacrificial trace structure using an additive forming method. The sacrificial trace structure having a geometry for the interconnect. The method continuous with forming a continuous seed metal layer on the sacrificial trace structure; and removing the sacrificial trace structure, wherein the continuous seed metal layer remains. An interconnect metal layer may be formed on the continuous seed layer. A dielectric material may then be formed on the interconnect metal layer to encapsulate a majority of the interconnect metal layer, wherein ends of the interconnect metal layer are exposed through one surface of the dielectric material to provide an interconnect extending into a dielectric material.Type: GrantFiled: November 21, 2017Date of Patent: May 14, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Daniel J. Buvid, Eric J. Campbell, Sarah K. Czaplewski, Christopher W. Steffen