Abstract: Hall effect devices and field effect transistors are formed incorporating a carbon-based nanostructure layer such as carbon nanotubes and/or graphene with a sacrificial metal layer formed there over to protect the carbon-based nanostructure layer during processing.

Abstract: Hall effect devices and field effect transistors are formed incorporating a carbon-based nanostructure layer such as carbon nanotubes and/or graphene with a sacrificial metal layer formed there over to protect the carbon-based nanostructure layer during processing.

Abstract: A method for forming nanostructures includes bonding a flexible substrate to a crystalline semiconductor layer having a two-dimensional material formed on a side opposite the flexible substrate. The crystalline semiconductor layer is stressed in a first direction to initiate first cracks in the crystalline semiconductor layer. The first cracks are propagated through the crystalline semiconductor layer and through the two-dimensional material. The stress of the crystalline semiconductor layer is released to provide parallel structures including the two-dimensional material on the crystalline semiconductor layer.

Abstract: A method for transfer of a two-dimensional material includes forming a spreading layer of a two-dimensional material on a first substrate. The spreading layer has at least one monolayer. A stressor layer is formed on the spreading layer. The stressor layer is configured to apply stress to a closest monolayer of the spreading layer. The closest monolayer is exfoliated by mechanically splitting the spreading layer wherein at least the closest monolayer remains on the stressor layer. The at least one monolayer is stamped against a second substrate to adhere remnants of the two-dimensional material on the at least one monolayer to the second substrate to provide a single monolayer on the stressor layer. The single monolayer is transferred to a third substrate.

Abstract: A method of forming an epitaxial semiconductor material that includes forming a graphene layer on a semiconductor and carbon containing substrate and depositing a metal containing monolayer on the graphene layer. An epitaxial layer of a gallium containing material is formed on the metal containing monolayer. A layered stack of the metal containing monolayer and the epitaxial layer of gallium containing material is cleaved from the graphene layer that is present on the semiconductor and carbon containing substrate.

Abstract: Interconnect structures including a graphene cap located on exposed surfaces of a copper structure are provided. In some embodiments, the graphene cap is located only atop the uppermost surface of the copper structure, while in other embodiments the graphene cap is located along vertical sidewalls and atop the uppermost surface of the copper structure. The copper structure is located within a dielectric material.

Abstract: In one embodiment, a multilayer graphene structure includes a first layer of graphene, a second layer of graphene; and an interstitial layer bonding the first layer of graphene to the second layer of graphene, wherein the interstitial layer comprises a polyaromatic compound. In another embodiment, a multilayer graphene structure is fabricated by providing a first layer of graphene, providing a second layer of graphene, and providing a first interstitial layer between the first layer of graphene and the second layer of graphene, wherein the first interstitial layer comprises a polyaromatic compound. In another embodiment, a multilayer graphene structure includes a plurality of layers of graphene and a plurality of interstitial layers formed of at least one polyaromatic compound, where each pair of the layers of graphene is bonded by one of the interstitial layers, such that a structure comprising alternating layers of graphene and interstitial layers is formed.

Abstract: In one embodiment, a multilayer graphene structure includes a first layer of graphene, a second layer of graphene; and an interstitial layer bonding the first layer of graphene to the second layer of graphene, wherein the interstitial layer comprises a polyaromatic compound. In another embodiment, a multilayer graphene structure is fabricated by providing a first layer of graphene, providing a second layer of graphene, and providing a first interstitial layer between the first layer of graphene and the second layer of graphene, wherein the first interstitial layer comprises a polyaromatic compound. In another embodiment, a multilayer graphene structure includes a plurality of layers of graphene and a plurality of interstitial layers formed of at least one polyaromatic compound, where each pair of the layers of graphene is bonded by one of the interstitial layers, such that a structure comprising alternating layers of graphene and interstitial layers is formed.

Abstract: Semiconductor structures including parallel graphene nanoribbons or carbon nanotubes oriented along crystallographic directions are provided from a template of silicon carbide (SiC) fins or nanowires. The SiC fins or nanowires are first provided and then graphene nanoribbons or carbon nanotubes are formed on the exposed surfaces of the fin or the nanowires by annealing. In embodiments in which closed carbon nanotubes are formed, the nanowires are suspended prior to annealing. The location, orientation and chirality of the graphene nanoribbons and the carbon nanotubes that are provided are determined by the corresponding silicon carbide fins and nanowires from which they are formed.

Abstract: A semiconductor-carbon alloy layer is formed on the surface of a semiconductor substrate, which may be a commercially available semiconductor substrate such as a silicon substrate. The semiconductor-carbon alloy layer is converted into at least one graphene layer during a high temperature anneal, during which the semiconductor material on the surface of the semiconductor-carbon alloy layer is evaporated selective to the carbon atoms. As the semiconductor atoms are selectively removed and the carbon concentration on the surface of the semiconductor-carbon alloy layer increases, the remaining carbon atoms in the top layers of the semiconductor-carbon alloy layer coalesce to form a graphene layer having at least one graphene monolayer. Thus, a graphene layer may be provided on a commercially available semiconductor substrate having a diameter of 200 mm or 300 mm.

Abstract: A method for transfer of a two-dimensional material includes forming a spreading layer of a two-dimensional material on a substrate, the spreading layer having a monolayer. A stressor layer is formed on the spreading layer, and the stressor layer is configured to apply stress to a closest monolayer of the spreading layer. The closest monolayer is exfoliated by mechanically splitting the spreading layer wherein the closest monolayer remains on the stressor layer.

Abstract: Semiconductor structures including parallel graphene nanoribbons or carbon nanotubes oriented along crystallographic directions are provided from a template of silicon carbide (SiC) fins or nanowires. The SiC fins or nanowires are first provided and then graphene nanoribbons or carbon nanotubes are formed on the exposed surfaces of the fin or the nanowires by annealing. In embodiments in which closed carbon nanotubes are formed, the nanowires are suspended prior to annealing. The location, orientation and chirality of the graphene nanoribbons and the carbon nanotubes that are provided are determined by the corresponding silicon carbide fins and nanowires from which they are formed.

Abstract: A method for forming nanostructures includes bonding a flexible substrate to a crystalline semiconductor layer having a two-dimensional material formed on a side opposite the flexible substrate. The crystalline semiconductor layer is stressed in a first direction to initiate first cracks in the crystalline semiconductor layer. The first cracks are propagated through the crystalline semiconductor layer and through the two-dimensional material. The stress of the crystalline semiconductor layer is released to provide parallel structures including the two-dimensional material on the crystalline semiconductor layer.

Abstract: A method for transfer of a two-dimensional material includes forming a spreading layer of a two-dimensional material on a first substrate. The spreading layer has at least one monolayer. A stressor layer is formed on the spreading layer. The stressor layer is configured to apply stress to a closest monolayer of the spreading layer. The closest monolayer is exfoliated by mechanically splitting the spreading layer wherein at least the closest monolayer remains on the stressor layer. The at least one monolayer is stamped against a second substrate to adhere remnants of the two-dimensional material on the at least one monolayer to the second substrate to provide a single monolayer on the stressor layer. The single monolayer is transferred to a third substrate.

Abstract: A semiconductor-carbon alloy layer is formed on the surface of a semiconductor substrate, which may be a commercially available semiconductor substrate such as a silicon substrate. The semiconductor-carbon alloy layer is converted into at least one graphene layer during a high temperature anneal, during which the semiconductor material on the surface of the semiconductor-carbon alloy layer is evaporated selective to the carbon atoms. As the semiconductor atoms are selectively removed and the carbon concentration on the surface of the semiconductor-carbon alloy layer increases, the remaining carbon atoms in the top layers of the semiconductor-carbon alloy layer coalesce to form a graphene layer having at least one graphene monolayer. Thus, a graphene layer may be provided on a commercially available semiconductor substrate having a diameter of 200 mm or 300 mm.

Abstract: A method for forming nanostructures includes bonding a flexible substrate to a crystalline semiconductor layer having a two-dimensional material formed on a side opposite the flexible substrate. The crystalline semiconductor layer is stressed in a first direction to initiate first cracks in the crystalline semiconductor layer. The first cracks are propagated through the crystalline semiconductor layer and through the two-dimensional material. The stress of the crystalline semiconductor layer is released to provide parallel structures including the two-dimensional material on the crystalline semiconductor layer.

Abstract: A method for forming nanostructures includes bonding a flexible substrate to a crystalline semiconductor layer having a two-dimensional material formed on a side opposite the flexible substrate. The crystalline semiconductor layer is stressed in a first direction to initiate first cracks in the crystalline semiconductor layer. The first cracks are propagated through the crystalline semiconductor layer and through the two-dimensional material. The stress of the crystalline semiconductor layer is released to provide parallel structures including the two-dimensional material on the crystalline semiconductor layer.

Abstract: A single crystalline silicon carbide layer can be grown on a single crystalline sapphire substrate. Subsequently, a graphene layer can be formed by conversion of a surface layer of the single crystalline silicon layer during an anneal at an elevated temperature in an ultrahigh vacuum environment. Alternately, a graphene layer can be deposited on an exposed surface of the single crystalline silicon carbide layer. A graphene layer can also be formed directly on a surface of a sapphire substrate or directly on a surface of a silicon carbide substrate. Still alternately, a graphene layer can be formed on a silicon carbide layer on a semiconductor substrate. The commercial availability of sapphire substrates and semiconductor substrates with a diameter of six inches or more allows formation of a graphene layer on a commercially scalable substrate for low cost manufacturing of devices employing a graphene layer.

Abstract: A method for transfer of a two-dimensional material includes forming a spreading layer of a two-dimensional material on a substrate, the spreading layer having a monolayer. A stressor layer is formed on the spreading layer, and the stressor layer is configured to apply stress to a closest monolayer of the spreading layer. The closest monolayer is exfoliated by mechanically splitting the spreading layer wherein the closest monolayer remains on the stressor layer.

Abstract: Semiconductor structures including parallel graphene nanoribbons or carbon nanotubes oriented along crystallographic directions are provided from a template of silicon carbide (SiC) fins or nanowires. The SiC fins or nanowires are first provided and then graphene nanoribbons or carbon nanotubes are formed on the exposed surfaces of the fin or the nanowires by annealing. In embodiments in which closed carbon nanotubes are formed, the nanowires are suspended prior to annealing. The location, orientation and chirality of the graphene nanoribbons and the carbon nanotubes that are provided are determined by the corresponding silicon carbide fins and nanowires from which they are formed.