Abstract: An apparatus comprises at least one transistor. The at least one transistor comprises a substrate, a graphene layer formed on the substrate, and first and second source/drain regions spaced apart relative to one another on the substrate. The graphene layer comprises at least a first portion and a second portion, the first portion being in contact with the first source/drain region and the second portion being in contact with the second source/drain region. One or more cuts are formed in at least one of the first and second portions of the graphene layer. The apparatus allows for lowered contact resistance in graphene/metal contacts.

Abstract: Interconnect structures including a graphene cap located on exposed surfaces of a copper structure are provided. In some embodiments, the graphene cap is located only atop the uppermost surface of the copper structure, while in other embodiments the graphene cap is located along vertical sidewalls and atop the uppermost surface of the copper structure. The copper structure is located within a dielectric material.

Abstract: Interconnect structures including a graphene cap located on exposed surfaces of a copper structure are provided. In some embodiments, the graphene cap is located only atop the uppermost surface of the copper structure, while in other embodiments the graphene cap is located along vertical sidewalls and atop the uppermost surface of the copper structure. The copper structure is located within a dielectric material.

Abstract: A single crystalline silicon carbide layer can be grown on a single crystalline sapphire substrate. Subsequently, a graphene layer can be formed by conversion of a surface layer of the single crystalline silicon layer during an anneal at an elevated temperature in an ultrahigh vacuum environment. Alternately, a graphene layer can be deposited on an exposed surface of the single crystalline silicon carbide layer. A graphene layer can also be formed directly on a surface of a sapphire substrate or directly on a surface of a silicon carbide substrate. Still alternately, a graphene layer can be formed on a silicon carbide layer on a semiconductor substrate. The commercial availability of sapphire substrates and semiconductor substrates with a diameter of six inches or more allows formation of a graphene layer on a commercially scalable substrate for low cost manufacturing of devices employing a graphene layer.

Abstract: A single crystalline silicon carbide layer can be grown on a single crystalline sapphire substrate. Subsequently, a graphene layer can be formed by conversion of a surface layer of the single crystalline silicon layer during an anneal at an elevated temperature in an ultrahigh vacuum environment. Alternately, a graphene layer can be deposited on an exposed surface of the single crystalline silicon carbide layer. A graphene layer can also be formed directly on a surface of a sapphire substrate or directly on a surface of a silicon carbide substrate. Still alternately, a graphene layer can be formed on a silicon carbide layer on a semiconductor substrate. The commercial availability of sapphire substrates and semiconductor substrates with a diameter of six inches or more allows formation of a graphene layer on a commercially scalable substrate for low cost manufacturing of devices employing a graphene layer.

Abstract: Methods of forming a semiconductor structure including a semiconductor nanowire or epitaxial semiconductor material which extends from at least a surface of source region and the drain region are provided. The methods include converting an upper portion of the source region and the drain region and the semiconductor nanowire or epitaxial semiconductor material into a continuous metal semiconductor alloy. The continuous metal semiconductor alloy includes a lower portion that is contained within an upper surface of each of the source region and the drain region, and a vertical pillar portion extending upwardly from the lower portion.

Abstract: An ultra low-k dielectric material layer is formed on a semiconductor substrate. In one embodiment, a grid of wires is placed at a distance above a top surface of the ultra low-k dielectric material layer and is electrically biased such that the total electron emission coefficient becomes 1.0 at the energy of electrons employed in electron beam curing of the ultra low-k dielectric material layer. In another embodiment, a polymeric conductive layer is formed directly on the ultra low-k dielectric material layer and is electrically biased so that the total electron emission coefficient becomes 1.0 at the energy of electrons employed in electron beam curing of the ultra low-k dielectric material layer. By maintaining the total electron emission coefficient at 1.0, charging of the substrate is avoided, thus protecting any device on the substrate from any adverse changes in electrical characteristics.

Abstract: A silicon nitride layer is provided on an uppermost surface of a graphene layer and then a hafnium dioxide layer is provided on an uppermost surface of the silicon nitride layer. The silicon nitride layer acts as a wetting agent for the hafnium dioxide layer and thus prevents the formation of discontinuous columns of hafnium dioxide atop the graphene layer. The silicon nitride layer and the hafnium dioxide layer, which collectively form a low EOT bilayer gate dielectric, exhibit continuous morphology atop the graphene layer.

Abstract: A semiconductor structure having a high Hall mobility is provided that includes a SiC substrate having a miscut angle of 0.1° or less and a graphene layer located on an upper surface of the SiC substrate. Also, provided are semiconductor devices that include a SiC substrate having a miscut angle of 0.1° or less and at least one graphene-containing semiconductor device located atop the SiC substrate. The at least one graphene-containing semiconductor device includes a graphene layer overlying and in contact with an upper surface of the SiC substrate.

Abstract: A semiconductor structure includes a first dielectric material including at least one first conductive region contained therein. The structure also includes at least one graphene containing semiconductor device located atop the first dielectric material. The at least one graphene containing semiconductor device includes a graphene layer that overlies and is in direct with the first conductive region. The structure further includes a second dielectric material covering the at least one graphene containing semiconductor device and portions of the first dielectric material. The second dielectric material includes at least one second conductive region contained therein, and the at least one second conductive region is in contact with a conductive element of the at least one graphene containing semiconductor device.

Abstract: The present disclosure provides a semiconductor structure including a nanoribbon-containing layer of alternating graphene nanoribbons separated by alternating insulating ribbons. The alternating graphene nanoribbons are parallel to a surface of an underlying substrate and, in some embodiments, might be oriented along crystallographic directions of the substrate. The alternating insulating ribbons may comprise hydrogenated graphene, i.e., graphane, fluorinated graphene, or fluorographene. The semiconductor structure mentioned above can be formed by selectively converting portions of an initial graphene layer into alternating insulating ribbons, while the non-converted portions of the initial graphene form the alternating graphene nanoribbons. Semiconductor devices such as, for example, field effect transistors, can be formed atop the semiconductor structure provided in the present disclosure.

Abstract: A semiconductor structure including an ordered array of parallel graphene nanoribbons located on a surface of a semiconductor substrate is provided using a deterministically assembled parallel set of nanowires as an etch mask. The deterministically assembled parallel set of nanowires is formed across a gap present in a patterned graphene layer utilizing an electric field assisted assembly process. A semiconductor device, such as a field effect transistor, can be formed on the ordered array of parallel graphene nanoribbons.

Abstract: A method for fabricating an ultra low dielectric constant material is disclosed. The method includes placing a substrate into a deposition reactor. A first precursor is flowed into the deposition reactor. The first precursor is a matrix precursor. A second precursor is flowed into the deposition reactor. The second precursor is a porogen precursor. A preliminary film is deposited onto the substrate based on the first and second precursors. The preliminary film includes Si, C, O, and H atoms. A first ultraviolet curing step is performed on the substrate including the preliminary film at a first temperature. At least a second ultraviolet curing step is performed on the substrate including the preliminary film at a second temperature.

Abstract: An ultra low-k dielectric material layer is formed on a semiconductor substrate. In one embodiment, a grid of wires is placed at a distance above a top surface of the ultra low-k dielectric material layer and is electrically biased such that the total electron emission coefficient becomes 1.0 at the energy of electrons employed in electron beam curing of the ultra low-k dielectric material layer. In another embodiment, a polymeric conductive layer is formed directly on the ultra low-k dielectric material layer and is electrically biased so that the total electron emission coefficient becomes 1.0 at the energy of electrons employed in electron beam curing of the ultra low-k dielectric material layer. By maintaining the total electron emission coefficient at 1.0, charging of the substrate is avoided, thus protecting any device on the substrate from any adverse changes in electrical characteristics.

Abstract: Semiconductor structures including parallel graphene nanoribbons or carbon nanotubes oriented along crystallographic directions are provided from a template of silicon carbide (SiC) fins or nanowires. The SiC fins or nanowires are first provided and then graphene nanoribbons or carbon nanotubes are formed on the exposed surfaces of the fin or the nanowires by annealing. In embodiments in which closed carbon nanotubes are formed, the nanowires are suspended prior to annealing. The location, orientation and chirality of the graphene nanoribbons and the carbon nanotubes that are provided are determined by the corresponding silicon carbide fins and nanowires from which they are formed.

Abstract: A semiconductor structure having a high Hall mobility is provided that includes a SiC substrate having a miscut angle of 0.1° or less and a graphene layer located on an upper surface of the SiC substrate. Also, provided are semiconductor devices that include a SiC substrate having a miscut angle of 0.1° or less and at least one graphene-containing semiconductor device located atop the SiC substrate. The at least one graphene-containing semiconductor device includes a graphene layer overlying and in contact with an upper surface of the SiC substrate.

Abstract: A semiconductor structure includes a first dielectric material including at least one first conductive region contained therein. The structure also includes at least one graphene containing semiconductor device located atop the first dielectric material. The at least one graphene containing semiconductor device includes a graphene layer that overlies and is in direct with the first conductive region. The structure further includes a second dielectric material covering the at least one graphene containing semiconductor device and portions of the first dielectric material. The second dielectric material includes at least one second conductive region contained therein, and the at least one second conductive region is in contact with a conductive element of the at least one graphene containing semiconductor device.

Abstract: A semiconductor-carbon alloy layer is formed on the surface of a semiconductor substrate, which may be a commercially available semiconductor substrate such as a silicon substrate. The semiconductor-carbon alloy layer is converted into at least one graphene layer during a high temperature anneal, during which the semiconductor material on the surface of the semiconductor-carbon alloy layer is evaporated selective to the carbon atoms. As the semiconductor atoms are selectively removed and the carbon concentration on the surface of the semiconductor-carbon alloy layer increases, the remaining carbon atoms in the top layers of the semiconductor-carbon alloy layer coalesce to form a graphene layer having at least one graphene monolayer. Thus, a graphene layer may be provided on a commercially available semiconductor substrate having a diameter of 200 mm or 300 mm.

Abstract: A semiconductor structure including an ordered array of parallel graphene nanoribbons located on a surface of a semiconductor substrate is provided using a deterministically assembled parallel set of nanowires as an etch mask. The deterministically assembled parallel set of nanowires is formed across a gap present in a patterned graphene layer utilizing an electric field assisted assembly process. A semiconductor device, such as a field effect transistor, can be formed on the ordered array of parallel graphene nanoribbons.

Abstract: A contact structure is disclosed in which a continuous metal semiconductor alloy is located within a via contained within a dielectric material. The continuous semiconductor metal alloy is in direct contact with an upper metal line of a first metal level located atop the continuous semiconductor metal alloy and at least a surface of each source and drain diffusion region located beneath the continuous metal semiconductor alloy. The continuous metal semiconductor alloy includes a lower portion that is contained within an upper surface of each source and drain region, and a vertical pillar portion extending upward from the lower portion.