Patents by Inventor Chuan-Yi Lin
Chuan-Yi Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8779572Abstract: A three dimensional (3D) stacked chip structure with chips having on-chip heat spreader and method of forming are described. A 3D stacked chip structure comprises a first die having a first substrate with a dielectric layer formed on a front surface. One or more bonding pads and a heat spreader may be simultaneously formed in the dielectric layer. The first die is bonded with corresponding bond pads on a surface of a second die to form a stacked chip structure. Heat generated in the stacked chip structure may be diffused to the edges of the stacked chip structure through the heat spreader.Type: GrantFiled: November 5, 2013Date of Patent: July 15, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chuan-Yi Lin, Ching-Chen Hao, Chen Cheng Chou, Sheng-Yuan Lin
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Patent number: 8742583Abstract: The formation of a seal ring in a semiconductor integrated circuit (IC) die is described. Through-silicon vias (TSVs) are typically formed in a semiconductor IC die to facilitate the formation of a three dimensional (3D) stacking die structure. The TSVs may be utilized to provide electrical connections between components in different dies of the 3D stacking die structure. A seal ring is formed in the inter-metal dielectric (IMD) layers of an IC die, enclosing an active circuit region. The real ring is formed prior to the formation of the TSVs, preventing moistures or other undesired chemical agents from diffusing into the active circuit region during the subsequent processes of forming TSVs.Type: GrantFiled: January 16, 2012Date of Patent: June 3, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chuan-Yi Lin, Ching-Chen Hao, Chen Cheng Chou, Sheng-Yuan Lin
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Publication number: 20140054761Abstract: A three dimensional (3D) stacked chip structure with chips having on-chip heat spreader and method of forming are described. A 3D stacked chip structure comprises a first die having a first substrate with a dielectric layer formed on a front surface. One or more bonding pads and a heat spreader may be simultaneously formed in the dielectric layer. The first die is bonded with corresponding bond pads on a surface of a second die to form a stacked chip structure. Heat generated in the stacked chip structure may be diffused to the edges of the stacked chip structure through the heat spreader.Type: ApplicationFiled: November 5, 2013Publication date: February 27, 2014Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chuan-Yi Lin, Ching-Chen Hao, Chen Cheng Chou, Sheng-Yuan Lin
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Patent number: 8609506Abstract: A three dimensional (3D) stacked chip structure with chips having on-chip heat spreader and method of forming are described. A 3D stacked chip structure comprises a first die having a first substrate with a dielectric layer formed on a front surface. One or more bonding pads and a heat spreader may be simultaneously formed in the dielectric layer. The first die is bonded with corresponding bond pads on a surface of a second die to form a stacked chip structure. Heat generated in the stacked chip structure may be diffused to the edges of the stacked chip structure through the heat spreader.Type: GrantFiled: November 19, 2012Date of Patent: December 17, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chuan-Yi Lin, Ching-Chen Hao, Chen Cheng Chou, Sheng-Yuan Lin
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Patent number: 8314483Abstract: A three dimensional (3D) stacked chip structure with chips having on-chip heat spreader and method of forming are described. A 3D stacked chip structure comprises a first die having a first substrate with a dielectric layer formed on a front surface. One or more bonding pads and a heat spreader may be simultaneously formed in the dielectric layer. The first die is bonded with corresponding bond pads on a surface of a second die to form a stacked chip structure. Heat generated in the stacked chip structure may be diffused to the edges of the stacked chip structure through the heat spreader.Type: GrantFiled: November 12, 2009Date of Patent: November 20, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chuan-Yi Lin, Ching-Chen Hao, Chen Cheng Chou, Sheng-Yuan Lin
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Publication number: 20120266857Abstract: The present invention discloses a barbeque grill lift cover structure comprising a combining base disposed separately at corresponding positions on both sides of the body, and a pair of link rods installed with an interval apart and at rear laterals of the combining base, and another end of the link rod is pivotally coupled to both sides of the cover separately to constitute the barbeque grill lift cover structure of the invention, and the link rods at both sides of the body and the cover can be pivotally coupled, such that when the cover is lifted open, the link rods are pivotally turned and guided to achieve a smooth lifting movement and maintain the lift cover stably.Type: ApplicationFiled: April 20, 2011Publication date: October 25, 2012Inventor: Chuan-Yi LIN
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Publication number: 20120112322Abstract: The formation of a seal ring in a semiconductor integrated circuit (IC) die is described. Through-silicon vias (TSVs) are typically formed in a semiconductor IC die to facilitate the formation of a three dimensional (3D) stacking die structure. The TSVs may be utilized to provide electrical connections between components in different dies of the 3D stacking die structure. A seal ring is formed in the inter-metal dielectric (IMD) layers of an IC die, enclosing an active circuit region. The real ring is formed prior to the formation of the TSVs, preventing moistures or other undesired chemical agents from diffusing into the active circuit region during the subsequent processes of forming TSVs.Type: ApplicationFiled: January 16, 2012Publication date: May 10, 2012Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chuan-Yi Lin, Ching-Chen Hao, Chen Cheng Chou, Sheng-Yuan Lin
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Patent number: 8168529Abstract: The formation of a seal ring in a semiconductor integrated circuit (IC) die is described. Through-silicon vias (TSVs) are typically formed in a semiconductor IC die to facilitate the formation of a three dimensional (3D) stacking die structure. The TSVs may be utilized to provide electrical connections between components in different dies of the 3D stacking die structure. A seal ring is formed in the inter-metal dielectric (IMD) layers of an IC die, enclosing an active circuit region. The real ring is formed prior to the formation of the TSVs, preventing moistures or other undesired chemical agents from diffusing into the active circuit region during the subsequent processes of forming TSVs.Type: GrantFiled: November 13, 2009Date of Patent: May 1, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chuan-Yi Lin, Ching-Chen Hao, Chen Cheng Chou, Sheng-Yuan Lin
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Publication number: 20110253194Abstract: A photoelectric conversion is capable of converting the light energy into electrical power, comprising a tempered glass layer, a lens module, a substrate and a heat sink unit, wherein the lens module is formed from a plurality of lens units, which locate at one side of the tempered glass layer. A gap is formed via a plurality of protruding poles located between the lens units and the tempered glass layer. The gap is filled with transparent rubbers. A plurality of receiving units is located one side of the substrate for dissipating heat energy from the receiving units. The light energy is converted through the receiving units into the electrical energy by focusing the light to the receiving units via the tempered glass layer and the lens module.Type: ApplicationFiled: April 14, 2010Publication date: October 20, 2011Inventors: Chien-Feng LIN, Cheng-Yu Huang, Te-Kai Ku, Chuan-Yi Lin
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Publication number: 20110253883Abstract: A light collector is capable of collecting a incident light, comprises a light condenser having an incident surface and an exit surface, a light reflecting unit having two end surfaces and a receiving unit, wherein the incident light enters through the incident surface of the light condenser and the light condenser alters an optical distance and an optical direction of the incident light so that the incident light is transmitted evenly to the exit surface of the light condenser. A reflecting layer is positioned inside the light reflecting unit, and the light condenser is positioned at one end surface of the light reflecting unit in order to receive the incident light from the exit surface. The receiving unit is used to receive the incident light exiting from the light reflecting unit so that a photoelectrical process is carried out and the incident light is converted into electrical energy.Type: ApplicationFiled: April 14, 2010Publication date: October 20, 2011Inventors: Chien-Feng LIN, Cheng-Yu Huang, Te-Kai Ku, Chuan-Yi Lin
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Patent number: 7825024Abstract: A method of forming a semiconductor device having a through-silicon via (TSV) is provided. A semiconductor device is provided having a first dielectric layer formed thereon. One or more dielectric layers are formed over the first dielectric layer, such that each of the dielectric layers have a stacking structure, wherein the stacking structures in the one or more dielectric layers are vertically aligned. The stacking structures may be, for example, metal rings. The stacking structures are then removed to form a first recess. A second recess is formed by extending the first recess into the substrate. The second recess is filled with a conductive material to form the TSV.Type: GrantFiled: November 25, 2008Date of Patent: November 2, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chuan-Yi Lin, Song-Bor Lee, Ching-Kun Huang, Sheng-Yuan Lin
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Publication number: 20100187671Abstract: The formation of a seal ring in a semiconductor integrated circuit (IC) die is described. Through-silicon vias (TSVs) are typically formed in a semiconductor IC die to facilitate the formation of a three dimensional (3D) stacking die structure. The TSVs may be utilized to provide electrical connections between components in different dies of the 3D stacking die structure. A seal ring is formed in the inter-metal dielectric (IMD) layers of an IC die, enclosing an active circuit region. The real ring is formed prior to the formation of the TSVs, preventing moistures or other undesired chemical agents from diffusing into the active circuit region during the subsequent processes of forming TSVs.Type: ApplicationFiled: November 13, 2009Publication date: July 29, 2010Inventors: Chuan-Yi Lin, Ching-Chen Hao, Chen Cheng Chou, Sheng-Yuan Lin
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Publication number: 20100187670Abstract: A three dimensional (3D) stacked chip structure with chips having on-chip heat spreader and method of forming are described. A 3D stacked chip structure comprises a first die having a first substrate with a dielectric layer formed on a front surface. One or more bonding pads and a heat spreader may be simultaneously formed in the dielectric layer. The first die is bonded with corresponding bond pads on a surface of a second die to form a stacked chip structure. Heat generated in the stacked chip structure may be diffused to the edges of the stacked chip structure through the heat spreader.Type: ApplicationFiled: November 12, 2009Publication date: July 29, 2010Inventors: Chuan-Yi Lin, Ching-Chen Hao, Chen Cheng Chou, Sheng-Yuan Lin
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Publication number: 20100130003Abstract: A method of forming a semiconductor device having a through-silicon via (TSV) is provided. A semiconductor device is provided having a first dielectric layer formed thereon. One or more dielectric layers are formed over the first dielectric layer, such that each of the dielectric layers have a stacking structure, wherein the stacking structures in the one or more dielectric layers are vertically aligned. The stacking structures may be, for example, metal rings. The stacking structures are then removed to form a first recess. A second recess is formed by extending the first recess into the substrate. The second recess is filled with a conductive material to form the TSV.Type: ApplicationFiled: November 25, 2008Publication date: May 27, 2010Inventors: Chuan-Yi Lin, Song-Bor Lee, Ching-Kun Huang, Sheng-Yuan Lin
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Patent number: 7645973Abstract: A solar-tracking power generating apparatus includes a plurality of sensing units having a directional light-extraction member each, a plurality of solar batteries associated with a light-gathering device each, and a solar trajectory simulation unit. Therefore, the solar-tracking power generating apparatus enables more accurate tracking of solar position and focusing of more sunlight on the solar batteries, so that the solar batteries could absorb more sunlight and convert the same into an increased amount of electric power.Type: GrantFiled: October 15, 2007Date of Patent: January 12, 2010Inventors: Chien-Feng Lin, Chuan-Yi Lin, Cheng-Min Chen
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Publication number: 20090095342Abstract: A solar-tracking power generating apparatus includes a plurality of sensing units having a directional light-extraction member each, a plurality of solar batteries associated with a light-gathering device each, and a solar trajectory simulation unit. Therefore, the solar-tracking power generating apparatus enables more accurate tracking of solar position and focusing of more sunlight on the solar batteries, so that the solar batteries could absorb more sunlight and convert the same into an increased amount of electric power.Type: ApplicationFiled: October 15, 2007Publication date: April 16, 2009Inventors: Chien-Feng Lin, Chuan-Yi Lin, Cheng-Min Chen
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Patent number: 7459756Abstract: Provided is a semiconductor device and a method for its fabrication. The device includes a semiconductor substrate, a first silicide in a first region of the substrate, and a second silicide in a second region of the substrate. The first silicide may differ from the second silicide. The first silicide and the second silicide may be an alloy silicide.Type: GrantFiled: August 29, 2006Date of Patent: December 2, 2008Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Chieh Lin, Wen-Chin Lee, Yee-Chia Yeo, Chuan-Yi Lin, Chenming Hu
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Patent number: 7271431Abstract: According to the present invention, the integrated circuit includes isolation field regions on a semiconductor substrate. Gate dielectrics are formed on a surface of a substrate. Gate electrodes are formed on the gate dielectrics. A photo resist is formed covering the active regions. Dummy patterns are selectively etched. A dummy substrate is selectively etched. The photo resist is then removed. A pair of spacers is formed along opposite sidewalls of the gate electrode and the gate dielectric. The source and drain are formed on the surface of said substrate and on opposite sides of the gate. Silicide is formed on the gate electrode, source, and drain. A layer of inter-level dielectric is then formed. A contact opening and metal wiring are then formed.Type: GrantFiled: June 25, 2004Date of Patent: September 18, 2007Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chuan-Yi Lin, Shien-Yang Wu, Yee-Chia Yeo
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Publication number: 20060286740Abstract: Provided is a semiconductor device and a method for its fabrication. The device includes a semiconductor substrate, a first silicide in a first region of the substrate, and a second silicide in a second region of the substrate. The first silicide may differ from the second silicide. The first silicide and the second silicide may be an alloy silicide.Type: ApplicationFiled: August 29, 2006Publication date: December 21, 2006Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun-Chieh LIN, Wen-Chin Lee, Yee-Chia Yeo, Chuan-Yi Lin, Chenming Hu
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Patent number: D656774Type: GrantFiled: April 20, 2011Date of Patent: April 3, 2012Assignee: Voka Enterprise Co., Ltd.Inventor: Chuan-Yi Lin