Patents by Inventor Chuichi Miyazaki

Chuichi Miyazaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7892949
    Abstract: To divide a semiconductor wafer by stealth dicing, a test pad in a cutting region and an alignment target are collectively arranged along one side in a width direction of the cutting region, and a laser beam for forming a modified region is irradiated to a position away in plane from the test pad and the alignment target Am. In this manner, defects in cutting shape in a cutting process of a semiconductor wafer using stealth dicing can be reduced or prevented.
    Type: Grant
    Filed: November 9, 2006
    Date of Patent: February 22, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshiyuki Abe, Chuichi Miyazaki, Hideo Mutou, Tomoko Higashino
  • Publication number: 20100308442
    Abstract: In a state where an adhesive tape is attached onto a main surface of a semiconductor wafer, a trench is formed in a rear surface of the semiconductor wafer. For forming the trench in the rear surface of the semiconductor wafer, after coating a resist film on the rear surface of the semiconductor wafer, the resist film is patterned by using the photolithography technology. The patterning of the resist film is performed so as not to leave the resist film in the region where the trench is to be formed. Then, the trench is formed in a predetermined region of the semiconductor wafer by the dry etching technology using the patterned resist film as a mask. Specifically, the trench is formed in the region near the dicing line.
    Type: Application
    Filed: June 8, 2010
    Publication date: December 9, 2010
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Yasuhiro NAKA, Naotaka TANAKA, Toshihide UEMATSU, Chuichi MIYAZAKI, Kazunari SUZUKI, Yasuyuki NAKAJIMA, Yoshiyuki ABE, Kenji KOHZU, Kosuke KITAICHI, Shinya OGANE
  • Publication number: 20100311205
    Abstract: The reliability of the semiconductor device which has the structure which stores a plurality of semiconductor chips with which plane sizes differ in the same sealing body in the state where they are accumulated via the insulating film which has adhesive property is improved. In the semiconductor device which has the structure which stores a plurality of semiconductor chips with which plane sizes differ in the same sealing body in the state where they are accumulated via DAF, thickness of DAF of the back surface of the uppermost semiconductor chip with which the control circuit was formed was made thicker than each of DAF of the back surface of the lower layer semiconductor chip with which the memory circuit was formed. Hereby, the defect that the bonding wire which connects the uppermost semiconductor chip and a wiring substrate contacts the main surface corner part of a lower layer semiconductor chip can be reduced.
    Type: Application
    Filed: July 29, 2010
    Publication date: December 9, 2010
    Inventors: Takashi KIKUCHI, Koichi KANEMOTO, Chuichi MIYAZAKI, Toshihiro SHIOTSUKI
  • Patent number: 7795741
    Abstract: A semiconductor device which stores a plurality of semiconductor chips, having planar sizes which differ, in the same sealing body in a state in which they are accumulated via an insulating film which has an adhesive property. In the semiconductor device, the thickness of DAF of the back surface of the uppermost semiconductor chip with which the control circuit is formed is thicker than each of DAF of the back surface of the lower layer semiconductor chip with which the memory circuit is formed.
    Type: Grant
    Filed: September 7, 2007
    Date of Patent: September 14, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Takashi Kikuchi, Koichi Kanemoto, Chuichi Miyazaki, Toshihiro Shiotsuki
  • Publication number: 20100213594
    Abstract: A semiconductor device having a structure in which the structure is laminated in many stages is made thin. A reforming area is formed by irradiating a laser beam, where a condensing point is put together with the inside of the semiconductor substrate of a semiconductor wafer. Then, after applying the binding material of liquid state to the back surface of a semiconductor wafer by a spin coating method, this is dried and a solid-like adhesive layer is formed. Then, a semiconductor wafer is divided into each semiconductor chip by making the above-mentioned reforming area into a division origin. By pasting up this semiconductor chip on the main surface of the other semiconductor chip by the adhesive layer of the back surface, a semiconductor device having a structure in which the semiconductor device is laminated in many stages is manufactured.
    Type: Application
    Filed: May 4, 2010
    Publication date: August 26, 2010
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Tomoko Higashino, Chuichi Miyazaki, Yoshiyuki Abe
  • Patent number: 7759224
    Abstract: A technique capable of stably releasing chips from a dicing tape, includes grinding a back surface of a semiconductor wafer, while adhering a pressure sensitive adhesive tape to a circuit forming surface of the semiconductor wafer formed with an integrated circuit, to achieve a predetermined thickness and forcibly oxidizing the back surface of the semiconductor wafer. Then, the pressure sensitive adhesive tape adhered to the circuit forming surface of the semiconductor wafer is released, and a dicing tape is adhered to the back surface of the semiconductor wafer. Further, the semiconductor wafer is divided by dicing it into individual chips, and then the back surface of the chip is pressed by way of the dicing tape, thereby releasing the chips from the dicing tape.
    Type: Grant
    Filed: July 9, 2008
    Date of Patent: July 20, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Chuichi Miyazaki, Yoshiyuki Abe, Toshihide Uematsu, Minoru Kimura, Kazunari Suzuki, Masao Odagiri, Hideyuki Suga, Manabu Takata
  • Patent number: 7737001
    Abstract: In a stealth dicing process for a semiconductor device with a low dielectric constant layer, the occurrence of poor appearance such as a defective shape or discoloration in the layer is reduced or prevented as follows. A low dielectric constant layer is formed in an interlayer insulating layer formed on the main surface of a semiconductor wafer. A laser beam is focused on the inside of the wafer from the reverse side of the wafer in order to form modified regions selectively. Each modified region is formed in a way to contact, or partially get into, the low dielectric constant layer. In this formation process, the semiconductor wafer is cooled by a cooling element. This reduces or prevents discoloration of the low dielectric constant layer which might occur due to the heat of a laser beam.
    Type: Grant
    Filed: June 1, 2006
    Date of Patent: June 15, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Yoshiyuki Abe, Chuichi Miyazaki
  • Publication number: 20090191667
    Abstract: A semiconductor device having a structure in which the structure is laminated in many stages is made thin. A reforming area is formed by irradiating a laser beam, where a condensing point is put together with the inside of the semiconductor substrate of a semiconductor wafer. Then, after applying the binding material of liquid state to the back surface of a semiconductor wafer by a spin coating method, this is dried and a solid-like adhesive layer is formed. Then, a semiconductor wafer is divided into each semiconductor chip by making the above-mentioned reforming area into a division origin. By pasting up this semiconductor chip on the main surface of the other semiconductor chip by the adhesive layer of the back surface, a semiconductor device having a structure in which the semiconductor device is laminated in many stages is manufactured.
    Type: Application
    Filed: March 23, 2009
    Publication date: July 30, 2009
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Tomoko HIGASHINO, Chuichi MIYAZAKI, Yoshiyuki ABE
  • Publication number: 20090121337
    Abstract: To divide a semiconductor wafer by stealth dicing, a test pad in a cutting region and an alignment target are collectively arranged along one side in a width direction of the cutting region, and a laser beam for forming a modified region is irradiated to a position away in plane from the test pad and the alignment target Am. In this manner, defects in cutting shape in a cutting process of a semiconductor wafer using stealth dicing can be reduced or prevented.
    Type: Application
    Filed: November 9, 2006
    Publication date: May 14, 2009
    Inventors: Yoshiyuki Abe, Chuichi Miyazaki, Hideo Mutou, Tomoko Higashino
  • Patent number: 7514294
    Abstract: The semiconductor device having the structure which laminated the chip in many stages is made thin. A reforming area is formed by irradiating a laser beam, where a condensing point is put together with the inside of the semiconductor substrate of a semiconductor wafer. Then, after applying the binding material of liquid state to the back surface of a semiconductor wafer by a spin coating method, this is dried and a solid-like adhesive layer is formed. Then, a semiconductor wafer is divided into each semiconductor chip by making the above-mentioned reforming area into a division origin. By pasting up this semiconductor chip on the main surface of an other semiconductor chip by the adhesive layer of the back surface, the semiconductor device having the structure for which the semiconductor chip was laminated by many stages is manufactured.
    Type: Grant
    Filed: August 9, 2006
    Date of Patent: April 7, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Tomoko Higashino, Chuichi Miyazaki, Yoshiyuki Abe
  • Publication number: 20080318362
    Abstract: After performing rough grinding to the back surface of a semiconductor wafer using the first grinding material (for example, particle size of polish fine powder from #320 to #360) and making the thickness of the semiconductor wafer, for example less than 140 ?m, less than 120 ?m, or less than 100 ?m, the back surface of the semiconductor wafer being performed fine finish grinding using the third grinding material (for example, particle size of polish fine powder from #3000 to #100000), the thickness of the semiconductor wafer becomes, for example less than 100 ?m, less than 80 ?m, or less than 60 ?m, and the relatively thin second crush layer, for example the second crush layer of the thickness of less than 0.5 ?m, less than 0.3 ?m, or less than 0.1 ?m is formed on the back surface of the semiconductor wafer.
    Type: Application
    Filed: July 16, 2004
    Publication date: December 25, 2008
    Inventors: Chuichi Miyazaki, Yoshiyuki Abe
  • Publication number: 20080286948
    Abstract: A technique capable of stably releasing chips from a dicing tape, includes grinding a back surface of a semiconductor wafer, while adhering a pressure sensitive adhesive tape to a circuit forming surface of the semiconductor wafer formed with an integrated circuit, to achieve a predetermined thickness and forcibly oxidizing the back surface of the semiconductor wafer. Then, the pressure sensitive adhesive tape adhered to the circuit forming surface of the semiconductor wafer is released, and a dicing tape is adhered to the back surface of the semiconductor wafer. Further, the semiconductor wafer is divided by dicing it into individual chips, and then the back surface of the chip is pressed by way of the dicing tape, thereby releasing the chips from the dicing tape.
    Type: Application
    Filed: July 9, 2008
    Publication date: November 20, 2008
    Inventors: Chuichi Miyazaki, Yoshiyuki Abe, Toshihide Uematsu, Minoru Kimura, Kazunari Suzuki, Masao Odagiri, Hideyuki Suga, Manabu Takata
  • Patent number: 7452787
    Abstract: A technique capable of stably releasing chips from a dicing tape, includes grinding a back surface of a semiconductor wafer, while adhering a pressure sensitive adhesive tape to a circuit forming surface of the semiconductor wafer formed with an integrated circuit, to achieve a predetermined thickness and forcibly oxidizing the back surface of the semiconductor wafer. Then, the pressure sensitive adhesive tape adhered to the circuit forming surface of the semiconductor wafer is released, and a dicing tape is adhered to the back surface of the semiconductor wafer. Further, the semiconductor wafer is divided by dicing it into individual chips, and then the back surface of the chip is pressed by way of the dicing tape, thereby releasing the chips from the dicing tape.
    Type: Grant
    Filed: December 23, 2004
    Date of Patent: November 18, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Chuichi Miyazaki, Yoshiyuki Abe, Toshihide Uematsu, Minoru Kimura, Kazunari Suzuki, Masao Odagiri, Hideyuki Suga, Manabu Takata
  • Publication number: 20080251897
    Abstract: The reliability of the semiconductor device which has the structure which stores a plurality of semiconductor chips with which plane sizes differ in the same sealing body in the state where they are accumulated via the insulating film which has adhesive property is improved. In the semiconductor device which has the structure which stores a plurality of semiconductor chips with which plane sizes differ in the same sealing body in the state where they are accumulated via DAF, thickness of DAF of the back surface of the uppermost semiconductor chip with which the control circuit was formed was made thicker than each of DAF of the back surface of the lower layer semiconductor chip with which the memory circuit was formed. Hereby, the defect that the bonding wire which connects the uppermost semiconductor chip and a wiring substrate contacts the main surface corner part of a lower layer semiconductor chip can be reduced.
    Type: Application
    Filed: September 7, 2007
    Publication date: October 16, 2008
    Inventors: Takashi Kikuchi, Koichi Kanemoto, Chuichi Miyazaki, Toshihiro Shiotsuki
  • Patent number: 7420284
    Abstract: A semiconductor device includes a semiconductor chip formed with connection terminals, an elastic structure interposed between a main surface of the chip and a wiring substrate formed with wirings connected at first ends thereof to the connection terminals, and bump electrodes connected to the other ends of the wirings. The connection terminals may be at a center part or in peripheral part(s) of the chip main surface and both the elastic structure and wiring substrate are not provided at locations of connection terminals. A resin body seals at least the connection terminals and the exposed first ends of wirings (leads). In a scheme in which the connection terminals are located in a peripheral part of the chip main surface, the wiring substrate protrudes beyond the chip boundary where the connection terminals are arranged, and the resin body shape is restricted by the protruding part of the wiring substrate.
    Type: Grant
    Filed: July 25, 2006
    Date of Patent: September 2, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Chuichi Miyazaki, Yukiharu Akiyama, Masnori Shibamoto, Tomoaki Kudaishi, Ichiro Anjoh, Kunihiko Nishi, Asao Nishimura, Hideki Tanaka, Ryosuke Kimoto, Kunihiro Tsubosaki, Akio Hasebe
  • Patent number: 7265035
    Abstract: To improve the reliability and yield of a thin-type semiconductor device as used for a stack-type flash memory, the semiconductor device is manufactured by upheaving each of semiconductor chips (semiconductor devices) obtained by dicing a semiconductor wafer on an adhesive sheet from a backside via the adhesive sheet using an upthrow jig to which ultrasonic vibration is applied so as not to break through the adhesive sheet, and by picking up each semiconductor chip.
    Type: Grant
    Filed: March 10, 2003
    Date of Patent: September 4, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Hiroshi Honma, Noriyuki Ooroku, Hitoshi Odashima, Toru Mita, Chuichi Miyazaki, Takashi Wada
  • Publication number: 20070141752
    Abstract: The lowering of the manufacturing yield of semiconductor products resulting from the contamination impurities from the back surface of a semiconductor wafer is suppressed. When making thin semiconductor wafer 1, the first crushing layer formed by grinding the back surface of semiconductor wafer 1 with the first and second abrasive which has fixed abrasive is removed. Thereby, the die strength after dividing or mostly dividing semiconductor wafer 1 and making a chip is secured. Then, from the back surface side of semiconductor wafer 1, laser beam 16 is irradiated in the predetermined region of the predetermined depth from the back surface of semiconductor wafer 1, and for example, second crushing layer 15 with the gettering function of less than 1.0 ?m, less than 0.5 ?m, or less than 0.1 ?m in thickness is formed newly.
    Type: Application
    Filed: December 14, 2006
    Publication date: June 21, 2007
    Inventors: Yoshiyuki Abe, Chuichi Miyazaki
  • Publication number: 20070114672
    Abstract: The miniaturization of the system in package which laminates a plurality of semiconductor chips on a wiring substrate via a die attach film is promoted. In the system in package (SiP) which laminates memory chips and microcomputer chip via die attach film on wiring substrate, by forming metal plate in the chip mounting region of wiring substrate, and mounting memory chip of an undermost layer on this metal plate, the flatness of the chip mounting region of wiring substrate is secured, and die attach film which intervenes between metal plate and memory chip of an undermost layer is made the same quality as die attach film which intervenes between chips (between memory chips and between memory chip and microcomputer chips), and the same thickness.
    Type: Application
    Filed: October 20, 2006
    Publication date: May 24, 2007
    Inventors: Tomoko Higashino, Hirotaka Nishizawa, Tamaki Wada, Chuichi Miyazaki
  • Patent number: 7202570
    Abstract: A semiconductor device having a superior connection reliability is obtained by providing a buffer body for absorbing the difference of thermal expansion between the mounting substrate and the semiconductor element in a semiconductor package structure, even if an organic material is used for the mounting substrate. A film material is used as the body for buffering the thermal stress generated by the difference in thermal expansion between the mounting substrate and the semiconductor element. The film material has modulus of elasticity of at least 1 MPa in the reflow temperature range (200–250° C.).
    Type: Grant
    Filed: December 1, 2003
    Date of Patent: April 10, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Akira Nagai, Shuji Eguchi, Masahiko Ogino, Masanori Segawa, Toshiak Ishii, Nobutake Tsuyuno, Hiroyoshi Kokaku, Rie Hattori, Makoto Morishima, Ichiro Anjoh, Kunihiro Tsubosaki, Chuichi Miyazaki, Makoto Kitano, Mamoru Mita, Norio Okabe
  • Publication number: 20070066044
    Abstract: In a stealth dicing process for a semiconductor device with a low dielectric constant layer, the occurrence of poor appearance such as a defective shape or discoloration in the layer is reduced or prevented as follows. A low dielectric constant layer is formed in an interlayer insulating layer formed on the main surface of a semiconductor wafer. A laser beam is focused on the inside of the wafer from the reverse side of the wafer in order to form modified regions selectively. Each modified region is formed in a way to contact, or partially get into, the low dielectric constant layer. In this formation process, the semiconductor wafer is cooled by a cooling element. This reduces or prevents discoloration of the low dielectric constant layer which might occur due to the heat of a laser beam.
    Type: Application
    Filed: June 1, 2006
    Publication date: March 22, 2007
    Inventors: Yoshiyuki Abe, Chuichi Miyazaki