Patents by Inventor Chun-Hsu Chen
Chun-Hsu Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20190088484Abstract: A method of fabricating a semiconductor structure includes providing a semiconductor substrate, forming a trench in the semiconductor substrate, overfilling the trench with a first semiconductor material, wherein the first semiconductor material does not have a dopant, forming a second semiconductor material on the first semiconductor material, wherein the second semiconductor material contains a dopant, and performing a thermal treatment so that the dopant in the second semiconductor material diffuses into the first semiconductor material to form a doped third semiconductor material in the trench.Type: ApplicationFiled: September 18, 2017Publication date: March 21, 2019Applicant: Vanguard International Semiconductor CorporationInventors: Chih-Ming KAO, Rong-Gen WU, Han-Wen CHANG, Chun-Hsu CHEN, Yu-Chun HO
-
Publication number: 20190088486Abstract: A manufacturing method of a semiconductor device includes the following steps. A first conductive layer, a first oxide layer, and a hardmask layer are sequentially formed on a substrate. The hardmask layer and the first oxide layer are patterned to form a stacking structure including a hardmask pattern and a first oxide pattern. An oxidation process is performed, such that a second oxide layer is formed on surfaces of the stacking structure and the first conductive layer, and a region of the first conductive layer adjacent to a sidewall of the stacking structure are oxidized to form an extending oxide pattern. The second oxide layer is removed. The stacking structure is applied as a mask to remove an exposed portion of the first conductive layer and the substrate therebelow, such that a first conductive structure and a recess in the substrate are formed. The stacking structure is removed. The extending oxide pattern is removed.Type: ApplicationFiled: August 27, 2018Publication date: March 21, 2019Applicant: Winbond Electronics Corp.Inventors: Chung-Hsien Liu, Chun-Hsu Chen, Lu-Ping Chiang
-
Publication number: 20190087375Abstract: A USB hub includes an upstream port; a first USB device control unit for performing packet format conversion; an FIFO circuit for storing data outputted from the first host; a second USB device control unit for performing packet format conversion; and a plurality of downstream ports. When any one of the downstream ports is coupled to the mobile device, if the first host commands the mobile device to switch to a host role from a device role, the mobile device temporarily disconnects from the USB hub, and the first host commands the USB hub to change an internal routing path. After the mobile device switches to the host role, the first host still performs the host role, and the first USB device control unit performs the device role; the mobile device performs the host role, and the second USB device control unit performs the device role.Type: ApplicationFiled: June 7, 2018Publication date: March 21, 2019Applicant: PROLIFIC TECHNOLOGY INC.Inventors: Tien-Wei YU, Cheng-Sheng CHAN, Chun-Hsu CHEN, Ren-Jie DUAN
-
Patent number: 10157930Abstract: A method for fabricating a memory device is provided. In the method, a first gate dielectric layer is formed on a substrate in a first region. A second gate dielectric layer is formed on the substrate in a second region and a third region. A first conductive layer is formed on the substrate. A first dielectric layer is directly formed on the first conductive layer. One portion of the first dielectric layer, one portion of the first conductive layer, and one portion of the second gate dielectric layer in the second region are removed. A third gate dielectric layer and a second conductive layer are formed sequentially on the substrate in the second region. A third conductive layer and a second dielectric layer are formed sequentially on the substrate. Isolation structures are formed in the substrate. Here, the isolation structures penetrate the second dielectric layer and extend into the substrate.Type: GrantFiled: November 16, 2016Date of Patent: December 18, 2018Assignee: Winbond Electronics Corp.Inventors: Chun-Hsu Chen, Hsu-Chi Cho
-
Publication number: 20180350608Abstract: A method of manufacturing a memory device including following steps is provided. A first dielectric layer and a first conductive layer are formed in order on the substrate. A first opening and a second opening on the first opening are formed in the substrate, the first dielectric layer and the first conductive layer. An isolation structure is formed in the first opening. A second dielectric layer is formed on the substrate to conformally cover a top surface of the first conductive layer and a surface of the second opening. A heat treatment is performed on the second dielectric layer to enhance the bonding between the second dielectric layer and the first conductive layer. An etching process is performed, so as to remove a portion of the second dielectric layer and expose a top surface of the isolation structure.Type: ApplicationFiled: January 11, 2018Publication date: December 6, 2018Applicant: Winbond Electronics Corp.Inventors: Chung-Hsien Liu, Chun-Hsu Chen, Lu-Ping Chiang
-
Publication number: 20180308929Abstract: A memory structure including a substrate, stacked structures, at least one isolation structure, a second conductive layer, and a second dielectric layer is provided. The stacked structures are disposed on the substrate. Each of the stacked structures includes a first dielectric layer and a first conductive layer sequentially disposed on the substrate. A first opening is located between two adjacent stacked structures, and the first opening extends into the substrate. The isolation structure is disposed in the first opening and covers a sidewall of the first dielectric layer. The isolation structure has a recess, such that a top profile of the isolation structure is shaped as a funnel. The second conductive layer is disposed on the stacked structures and fills the first opening. The second dielectric layer is disposed between the second conductive layer and the first conductive layer.Type: ApplicationFiled: August 30, 2017Publication date: October 25, 2018Applicant: Winbond Electronics Corp.Inventors: Chung-Hsien Liu, Chun-Hsu Chen, Lu-Ping Chiang
-
Publication number: 20180061848Abstract: A method for fabricating a memory device is provided. In the method, a first gate dielectric layer is formed on a substrate in a first region. A second gate dielectric layer is formed on the substrate in a second region and a third region. A first conductive layer is formed on the substrate. A first dielectric layer is directly formed on the first conductive layer. One portion of the first dielectric layer, one portion of the first conductive layer, and one portion of the second gate dielectric layer in the second region are removed. A third gate dielectric layer and a second conductive layer are formed sequentially on the substrate in the second region. A third conductive layer and a second dielectric layer are formed sequentially on the substrate. Isolation structures are formed in the substrate. Here, the isolation structures penetrate the second dielectric layer and extend into the substrate.Type: ApplicationFiled: November 16, 2016Publication date: March 1, 2018Applicant: Winbond Electronics Corp.Inventors: Chun-Hsu Chen, Hsu-Chi Cho
-
Patent number: 8100729Abstract: A cable connector includes a connecting head, a wiring assembly and a cable. The cable is assembled with the wiring assembly, and then the wiring assembly is assembled with the connecting head, thereby forming a cable connector. The wiring assembly has a rear-half portion and a front-half portion that are connected to each other. The distal end of the rear-half portion is recessed to form a plurality of wiring ports. The interior of each wiring port is provided with a plurality of cable troughs. The cable troughs extend toward the front-half portion to form a plurality of wiring slots on the front-half portion.Type: GrantFiled: May 11, 2010Date of Patent: January 24, 2012Assignee: Jess-Link Products Co., Ltd.Inventors: Chun-Hsu Chen, Chun-Hua Chen
-
Patent number: 8053667Abstract: A housing of a Quad Small Form-Factor Pluggable transceiver module includes a metallic casing and a plurality of elastic grounding assemblies. The metallic casing has a lower casing, a plurality of partitions and an upper casing. The lower casing is connected to the upper casing. The partitions are provided between the lower casing and the upper casing at intervals, thereby separating the interior of the metallic casing into a plurality of accommodating spaces. The accommodating spaces each receives a connector of a transceiver module, thereby forming a plurality of ports. Thus, the connectors of the transceiver modules share the common housing, thereby reducing the occupied space on the circuit board and increasing the number of the transceiver modules arranged on the circuit board.Type: GrantFiled: July 23, 2008Date of Patent: November 8, 2011Assignee: Jess-Link Products Co., Ltd.Inventors: Chun-Hua Chen, Chun-Hsu Chen
-
Patent number: 7914336Abstract: A wiring process of a cable connector includes the steps of: providing a cable and a wiring assembly for the cable connector, the wiring assembly having a wiring body and a wiring plate; inserting naked ends of each cable core extending from the distal end of the cable into wiring ports of the wiring plate separately; and assembling the wiring plate with the wiring body to form the wiring assembly, thereby completing the wiring process.Type: GrantFiled: May 11, 2010Date of Patent: March 29, 2011Assignee: Jess-Link Products Co., Ltd.Inventors: Chun-Hsu Chen, Chun-Hua Chen
-
Publication number: 20100304615Abstract: A cable connector includes a connecting head, a wiring assembly and a cable. The cable is assembled with the wiring assembly, and then the wiring assembly is assembled with the connecting head, thereby forming a cable connector. The wiring assembly has a rear-half portion and a front-half portion that are connected to each other. The distal end of the rear-half portion is recessed to form a plurality of wiring ports. The interior of each wiring port is provided with a plurality of cable troughs. The cable troughs extend toward the front-half portion to form a plurality of wiring slots on the front-half portion.Type: ApplicationFiled: May 11, 2010Publication date: December 2, 2010Inventors: Chun-Hsu CHEN, Chun-Hua Chen
-
Publication number: 20100304616Abstract: A wiring process of a cable connector includes the steps of: providing a cable and a wiring assembly for the cable connector, the wiring assembly having a wiring body and a wiring plate; inserting naked ends of each cable core extending from the distal end of the cable into wiring ports of the wiring plate separately; and assembling the wiring plate with the wiring body to form the wiring assembly, thereby completing the wiring process.Type: ApplicationFiled: May 11, 2010Publication date: December 2, 2010Inventors: Chun-Hsu CHEN, Chun-Hua Chen
-
Publication number: 20100199022Abstract: An information access method and a computer system are provided. The computer system includes a system management bus (SMBus), a non-volatile memory, a plurality of hardware devices, a chipset, and a CPU. The hardware devices have a plurality of specific recognition information. The CPU performs a configuration process on the hardware devices through the chipset according to the standard for a SMBus protocol, so as to distribute a plurality of memory spaces in the non-volatile memory to the hardware devices. The hardware devices share the SMBus for accessing the plurality of specific recognition information in the memory spaces.Type: ApplicationFiled: March 10, 2009Publication date: August 5, 2010Applicant: VIA TECHNOLOGIES, INC.Inventors: Chun-Hsu Chen, Chung-Ching Huang, Chin-Han Chang
-
Publication number: 20100018738Abstract: A housing of a Quad Small Form-Factor Pluggable transceiver module includes a metallic casing and a plurality of elastic grounding assemblies. The metallic casing has a lower casing, a plurality of partitions and an upper casing. The lower casing is connected to the upper casing. The partitions are provided between the lower casing and the upper casing at intervals, thereby separating the interior of the metallic casing into a plurality of accommodating spaces. The accommodating spaces each receives a connector of a transceiver module, thereby forming a plurality of ports. Thus, the connectors of the transceiver modules share the common housing, thereby reducing the occupied space on the circuit board and increasing the number of the transceiver modules arranged on the circuit board.Type: ApplicationFiled: July 23, 2008Publication date: January 28, 2010Inventors: Chun-Hua Chen, Chun-Hsu Chen
-
Patent number: 7590874Abstract: An over-heat protecting circuit and a system circuit board thereof are disclosed. The over-heat protecting circuit receives a voltage-detecting signal, a control signal, and an over-heat signal, and comprises a first logic circuit, a memory circuit, and a second logic circuit. The first logic circuit receives and processes the voltage-detecting signal and the over-heat signal to output a first logic signal. The memory circuit receives and processes the first logic signal and the control signal to output a latching signal. The second logic circuit receives and processes the latching signal and the control signal to output a power-control signal. Eventually, the power supplier stops outputting an operating voltage according to the power-control signal.Type: GrantFiled: July 21, 2006Date of Patent: September 15, 2009Assignee: Mitac International CorporationInventor: Chun-Hsu Chen
-
Patent number: 7501717Abstract: A universal driving apparatus of a computer system inputs two control signals of two different duty cycles through a speed control pin of a receptacle for connecting fans with the electricity supplied continuously. The differentiation percentage of the two speeds is compared with a threshold to identify the fan types. Therefore the computer system is capable of driving the identified fan correctly according to the result of the fan-type identification.Type: GrantFiled: May 18, 2006Date of Patent: March 10, 2009Assignee: Tyan Computer CorporationInventor: Chun-Hsu Chen
-
Patent number: 7476117Abstract: An electrical connector includes a latch and an activating piece. The latch has at least one hook and a slope. A fulcrum is formed between the hook and the slope. The hook can be combined with an open hole of a guiding frame. The activating piece has an annular structure and a slope structure. The slope structure is provided on the slope. By pulling or releasing the annular structure, the slope structure can push or be separated from the slope. Via the lever principle, the latch makes the hook to ascend or descend. In this way, the electrical connector can be separated from or connected with a corresponding female electrical connector in the guiding frame more easily. Further, the structure of the electrical connector is simple, thereby reducing the manufacturing cost and facilitating the manufacturing and assembling process.Type: GrantFiled: May 15, 2008Date of Patent: January 13, 2009Assignee: Jess-Link Products Co., Ltd.Inventors: Chun-Hua Chen, Chun-Hsu Chen
-
Publication number: 20070294436Abstract: An apparatus and a method are provided to scan the slave addresses of plural slave devices connected to a system management bus (SMBus). By means of signal simulation corresponsive to an address section of SMBus Packet Protocols, a scan process unit of the apparatus generates plural scan packets and sends to the SMBus for plural address acknowledgements from the corresponding slave devices. Therefore, the distribution of the slave addresses may be easily discovered by the scan method without causing any malfunction of the slave devices.Type: ApplicationFiled: March 12, 2007Publication date: December 20, 2007Inventors: Ming-Feng CHEN, Chun-Hsu CHEN
-
Publication number: 20070214373Abstract: An over-heat protecting circuit and a system circuit board thereof are disclosed. The over-heat protecting circuit receives a voltage-detecting signal, a control signal, and an over-heat signal, and comprises a first logic circuit, a memory circuit, and a second logic circuit. The first logic circuit receives and processes the voltage-detecting signal and the over-heat signal to output a first logic signal. The memory circuit receives and processes the first logic signal and the control signal to output a latching signal. The second logic circuit receives and processes the latching signal and the control signal to output a power-control signal. Eventually, the power supplier stops outputting an operating voltage according to the power-control signal.Type: ApplicationFiled: July 21, 2006Publication date: September 13, 2007Inventor: Chun-Hsu Chen
-
Patent number: 7226307Abstract: A plug connector for plugging with a mating connector includes a lower housing, an upper housing fixed on the lower housing, a disengaged member and a covering lid. The upper housing has a receiving cavity concaved from its top surface and a pivotal groove formed in the receiving cavity. The disengaged member has a main body, an elastic member disposed on the main body, a handle portion extending and inclining upwardly from the main body, and a hooking plate extending from the main body. The hooking plate is opposite to the handle portion and is exposed outside the upper housing. The main body forms a rod-shaped portion disposed movably in the pivotal groove. The hooking plate hooks elastically the mating connector. The covering lid is fixed on the upper housing and covers the receiving cavity. The elastic member is propped against a bottom surface of the covering lid.Type: GrantFiled: July 27, 2006Date of Patent: June 5, 2007Assignee: Jess-Link Products Co., Ltd.Inventors: Shi-Jung Chen, Chun-Hsu Chen