Abstract: Semiconductor packages and methods of forming the same are provided. a semiconductor package includes a sub-package, a second die and a second molding layer. The sub-package includes a first die, a first molding layer aside the first die and a first redistribution layer structure disposed over the first die and the first molding layer and electrically connected to the first die. The second die is disposed over the sub-package, wherein the first die and the second die are disposed on opposite surfaces of the first redistribution layer structure. The second molding layer encapsulates the sub-package and the second die.

Abstract: One of semiconductor packages includes a substrate and a package structure. The package structure is bonded to the substrate and includes a first redistribution layer structure, a first logic die, a plurality of second logic dies, a first memory die, a first heat conduction block and a first encapsulant. The first logic die and the second logic dies are disposed over and electrically connected to the first redistribution layer structure. The first memory die is disposed over the first logic die and the second logic dies and electrically connected to first redistribution layer structure. The first heat conduction block is disposed over the first logic die and the second logic dies. The first encapsulant encapsulates the first memory die and the first heat conduction block.

Abstract: A semiconductor package includes a chip, a redistribution structure, and first under-ball metallurgies patterns. The chip includes conductive posts exposed at an active surface. The redistribution structure is disposed on the active surface. The redistribution structure includes a first dielectric layer, a topmost metallization layer, and a second dielectric layer. The first dielectric layer includes first openings exposing the conductive posts of the chip. The topmost metallization layer is disposed over the first dielectric layer and is electrically connected to the conductive posts. The topmost metallization layer comprises first contact pads and routing traces connected to the first contact pads. The second dielectric layer is disposed on the topmost metallization layer and includes second openings exposing the first contact pads. The first under-ball metallurgies patterns are disposed on the first contact pads, extending on and contacting sidewalls and top surfaces of the first contact pads.

Abstract: In an embodiment, a device includes: a first device including: an integrated circuit device having a first connector; a first photosensitive adhesive layer on the integrated circuit device; and a first conductive layer on the first connector, the first photosensitive adhesive layer surrounding the first conductive layer; a second device including: an interposer having a second connector; a second photosensitive adhesive layer on the interposer, the second photosensitive adhesive layer physically connected to the first photosensitive adhesive layer; and a second conductive layer on the second connector, the second photosensitive adhesive layer surrounding the second conductive layer; and a conductive connector bonding the first and second conductive layers, the conductive connector surrounded by an air gap.

Abstract: A package-on-package structure including a first and second package is provided. The first package includes a first semiconductor die, a plurality of conductive pins, an insulating encapsulant, a backside connection structure and a redistribution layer. The conductive pins are surrounding the first semiconductor die and have a base portion with a first width and a body portion with a second width, the base portion is connected to the body portion and the first width being larger than the second width. The insulating encapsulant is encapsulating the first semiconductor die and the conductive pins. The backside connection structure is disposed on the first semiconductor die and electrically connected to the conductive pins. The redistribution layer is disposed on the first semiconductor die, and electrically connected to the first semiconductor die and the conductive pins. The second package is stacked on the first package and electrically connected to the backside connection structure.

Abstract: Chip package structures are provided. The chip package structure includes a protection layer and a first chip disposed over the protection layer. The chip package structure further includes a first photosensitive layer formed around sidewalls of the first chip and covering a top surface of the first chip and a second chip disposed over the first photosensitive layer. In addition, the first chip and the second chip are separated by the first photosensitive layer.

Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package at least has chip and a redistribution layer. The redistribution layer is disposed on the chip. The redistribution layer includes joining portions having first pads and second pads surrounding the chip. The first pads are arranged around a location of the chip and the second pads are arranged over the location of the chip. The second pads located closer to the chip are narrower than the first pads located further away from the chip.

Abstract: In an embodiment, a device includes: a first device including: an integrated circuit device having a first connector; a first photosensitive adhesive layer on the integrated circuit device; and a first conductive layer on the first connector, the first photosensitive adhesive layer surrounding the first conductive layer; a second device including: an interposer having a second connector; a second photosensitive adhesive layer on the interposer, the second photosensitive adhesive layer physically connected to the first photosensitive adhesive layer; and a second conductive layer on the second connector, the second photosensitive adhesive layer surrounding the second conductive layer; and a conductive connector bonding the first and second conductive layers, the conductive connector surrounded by an air gap.

Abstract: Methods and apparatus for integrating a CMOS image sensor and an image signal processor (ISP) together using an interposer to form a system in package device module are disclosed. The device module may comprise an interposer with a substrate. An interposer contact is formed within the substrate. A sensor device may be bonded to a surface of the interposer, wherein a sensor contact is bonded to a first end of the interposer contact. An ISP may be connected to the interposer, by bonding an ISP contact in the ISP to a second end of the interposer contact. An underfill layer may fill a gap between the interposer and the ISP. A printed circuit board (PCB) may further be connected to the interposer by way of a solder ball connected to another interposer contact. A thermal interface material may be in contact with the ISP and the PCB.

Abstract: A semiconductor package includes a semiconductor package, a cap, a seal, and microstructures. The semiconductor package includes at least one semiconductor die. The cap is disposed over an upper surface of the semiconductor package. The seal is located on the semiconductor package and between the cap and the semiconductor package. The cap includes an inflow channel and an outflow channel. The active surface of the at least one semiconductor die faces away from the cap. The cap and an upper surface of the semiconductor package define a circulation recess providing fluidic communication between the inflow channel and the outflow channel. The seal is disposed around the circulation recess. The microstructures are located within the circulation recess, and the microstructures are connected to at least one of the cap and the at least one semiconductor die.

Abstract: A semiconductor package has at least one die, a first redistribution layer and a second redistribution layer. The first redistribution layer includes a first dual damascene redistribution pattern having a first via portion and a first routing portion. The second redistribution layer is disposed on the first redistribution layer and over the first die and electrically connected with the first redistribution layer and the first die. The second redistribution layer includes a second dual damascene redistribution pattern having a second via portion and a second routing portion. A location of the second via portion is aligned with a location of first via portion.

Abstract: A package structure and a method of forming the same are provided. The package structure includes a die, an encapsulant, a first polymer material layer, a second polymer material layer and a first redistribution layer. The encapsulant encapsulates sidewalls of the die. The first polymer material layer is on the encapsulant and the die. The second polymer material layer is on the first polymer material layer. The first redistribution layer is embedded in the first polymer material layer and the second polymer material layer and electrically connected to the die. The first redistribution layer has a top surface substantially coplanar with a top surface of the second polymer material layer, and a portion of a top surface of the first polymer material layer is in contact with the first redistribution layer.

Abstract: Provided is a package including a die, a redistribution layer (RDL) structure, and a plurality of conductive connectors. The RDL structure includes a dielectric layer, a conductive feature, and a protective layer. The conductive feature is disposed in the dielectric layer and electrically connected to the die. The protective layer is disposed between the dielectric layer and the conductive feature. The protective layer, the dielectric layer, and the conductive feature have different materials. The plurality of conductive connectors are electrically connected to the die through the RDL structure.

Abstract: An integrated fan-out package includes an integrated circuit, a plurality of semiconductor devices, a first redistribution circuit structure, and an insulating encapsulation. The integrated circuit has an active surface and a rear surface opposite to the active surface. The semiconductor devices are electrically connected the integrated circuit. The first redistribution circuit structure is disposed between the integrated circuit and the semiconductor devices. The first redistribution circuit structure is electrically connected to the integrated circuit and the semiconductor devices respectively. The first redistribution circuit structure has a first surface, a second surface opposite to the first surface, and lateral sides between the first surface and the second surface. The insulating encapsulation encapsulates the integrated circuit and the semiconductor devices and covers the first surface and the second surface of the first redistribution circuit structure.

Abstract: Semiconductor packages and methods of forming the same are provided. a semiconductor package includes a sub-package, a second die and a second molding layer. The sub-package includes a first die, a first molding layer aside the first die and a first redistribution layer structure disposed over the first die and the first molding layer and electrically connected to the first die. The second die is disposed over the sub-package, wherein the first die and the second die are disposed on opposite surfaces of the first redistribution layer structure. The second molding layer encapsulates the sub-package and the second die.

Abstract: In an embodiment, a device includes: a first device including: an integrated circuit device having a first connector; a first photosensitive adhesive layer on the integrated circuit device; and a first conductive layer on the first connector, the first photosensitive adhesive layer surrounding the first conductive layer; a second device including: an interposer having a second connector; a second photosensitive adhesive layer on the interposer, the second photosensitive adhesive layer physically connected to the first photosensitive adhesive layer; and a second conductive layer on the second connector, the second photosensitive adhesive layer surrounding the second conductive layer; and a conductive connector bonding the first and second conductive layers, the conductive connector surrounded by an air gap.

Abstract: A semiconductor package has at least one die, a first redistribution layer and a second redistribution layer. The first redistribution layer includes a first dual damascene redistribution pattern having a first via portion and a first routing portion. The second redistribution layer is disposed on the first redistribution layer and over the first die and electrically connected with the first redistribution layer and the first die. The second redistribution layer includes a second dual damascene redistribution pattern having a second via portion and a second routing portion. A location of the second via portion is aligned with a location of first via portion.

Abstract: A package-on-package structure including a first and second package is provided. The first package includes a first semiconductor die, a plurality of conductive pins, an insulating encapsulant, a backside connection structure and a redistribution layer. The conductive pins are surrounding the first semiconductor die and have a base portion with a first width and a body portion with a second width, the base portion is connected to the body portion and the first width being larger than the second width. The insulating encapsulant is encapsulating the first semiconductor die and the conductive pins. The backside connection structure is disposed on the first semiconductor die and electrically connected to the conductive pins. The redistribution layer is disposed on the first semiconductor die, and electrically connected to the first semiconductor die and the conductive pins. The second package is stacked on the first package and electrically connected to the backside connection structure.

Abstract: A package structure and a method of forming the same are provided. The package structure includes a die, an encapsulant, and an RDL structure. The encapsulant is laterally encapsulating the die. The RDL structure is electrically connected to the die. The RDL structure includes a first dielectric layer, a first RDL, a second dielectric layer and a second RDL. The first dielectric layer is disposed on the encapsulant and the die. The first RDL is embedded in the first dielectric layer. The first RDL includes a first via and a first trace connected to each other. A top surface of the first RDL is coplanar with a top surface of the first dielectric layer. The second dielectric layer is on the first dielectric layer and the first RDL. The second RDL is embedded in the second dielectric layer and includes a second via and a second trace connected to each other. A top surface of the second RDL is coplanar with a top surface of the second dielectric layer. The second via is stacked directly on the first via.

Abstract: A semiconductor package structure includes a plurality of first dies spaced from each other, a molding layer between the first dies, a second die over the plurality of first dies and the molding layer, and an adhesive layer between the plurality of first dies and the second die, and between the molding layer and the second die. A first interface between the adhesive layer and the molding layer and a second interface between the adhesive layer and the plurality of first dies are at different levels.