Abstract: A multi-layer stacked chip package is provided. A first substrate, a first circuit layer, a first chip, and a first insulation layer form a lower layer chip package while a second substrate, a second circuit layer, a second chip, and a second insulation layer form an upper layer chip package. The upper layer chip package is stacked over the lower layer chip package so that the multi-layer stacked chip package is formed by such stacking mode. One of the at least two chips is used to operate the rest chips or computing functions of the respective chips are combined to increase overall computing performance.

Abstract: A chip package which includes a chip, at least one first dielectric layer, at least one second dielectric layer, at least one conductive circuit, and at least one third dielectric layer is provide. The conductive circuit is formed by highly concentrated silver paste or copper paste filled in at least one first groove of the first dielectric layer and at least one second groove of the second dielectric layer while at least one die pad of the chip is electrically connected with the conductive circuit for improving electrical conduction efficiency of the conductive circuit. Moreover, at least one die-pad bump is formed in the first groove, arranged at and electrically connected with a surface of the die pad for protecting of the die pad.

Abstract: A chip package and a method of manufacturing the same are provided. The chip package includes at least one insulating protective layer disposed on a periphery of a surface of a seed layer correspondingly. A plurality of insulating protective layers is arranged at the seed layer of a plurality of rectangular chips of a wafer and located corresponding to a plurality of dicing streets. Thereby cutting tools only cut the insulating protective layer, without cutting a thick metal layer during cutting process. The insulating protective layer is formed on a periphery of the thick metal layer of the chip package after the cutting process.

Abstract: A bump of a chip package with higher bearing capacity in wire bonding is provided. The at least one bump of the chip package is a metal stacked member with a certain thickness. An overall thickness of the bump is 4.5-20 ?m. Thereby a structural strength of the bump is improved and thus able to bear positive pressure generated in wire bonding or formation of a first bonding point. Thus at least one internal circuit of a chip will not be damaged by the positive pressure and allowed to pass through an area under at least one die pad or arrange under the die pad of the chip. Thereby increased cost problem caused by internal circuit redesign of the chip can be solved and this helps to reduce cost at manufacturing end.

Abstract: A blockchain-based carbon neutral transaction processing method includes following steps. An electricity sensor of each of a plurality of blockchain nodes of a blockchain system generates a local electricity information. After the electricity sensor generates the local electricity information, the blockchain system verifies whether the local electricity information of each of the blockchain nodes is correct. If the blockchain system verifies that the local electricity information of each of the blockchain nodes is correct, the blockchain system uploads the local electricity information of each of the blockchain nodes to a blockchain network of the blockchain system.

Abstract: A chip package with higher bearing capacity in wire bonding is provided. The chip package includes at least one conductive circuit which is a structure with a thickness ranging from 4.5 ?m to 20 ?m. Thereby a structural strength of the conductive circuit is improved and able to stand a positive pressure generated in wire bonding or formation of a first bonding point. Thus at least one internal circuit of a chip will not be damaged by the positive pressure and allowed to pass through an area under the first bonding point or arrange under the first bonding point. A problem of increased cost at manufacturing end caused by the internal circuit redesign of the chip can be solved effectively. This is beneficial to cost reduction at manufacturing end.

Abstract: The present application discloses an integration package with insulating boards, which features an insulating board structure replacing a plurality of printed circuit boards and packaging materials in a conventional POP structure and comprises a base substrate, a basic circuit and at least an electronic component: the basic circuit is exposed on an upper surface of the base substrate; the electronic component and the basic circuit are electrically connected with each other; both the base substrate and the electronic component are thermally compressed and covered by a first insulating board.

Abstract: A method for extracting road data comprises obtaining ground data from first environment detection data of a detected region, obtaining a first ground model using the ground data, filling a missing region of the first ground model to obtain a second ground model, obtaining road attributes of the detected region according to the second ground model, performing road damage recognition using second environment detection data of the detected region and the second ground model, and storing the road attributes and the result of the road damage recognition as pieces of road data of the detected region.

Abstract: The present application describes a system in package which features no printed circuit board inside an encapsulation structure and comprises: a copper holder with a silicon layer at a top face; a plurality of dies mounted on the silicon layer and electrically connected to a plurality of data pins of the copper holder; a passive element mounted on the silicon layer and electrically connected to the dies wherein the dies are electrically connected to the ground pin of the copper holder; a molding compound encasing the dies and the passive element on the top face of the copper holder.

Abstract: A managing method of a fragmentary digital creation incorporated with a creation managing platform is disclosed. The method includes: receiving an uploaded digital creation by the creation managing platform; receiving a setting command to set a charging approach, a price and a profit-sharing mode of the digital creation; generating a text record corresponding to content of the digital creation through an algorithm; analyzing the digital creation through an AI model to divide the digital creation into multiple fragmentary creations; labeling each fragmentary creation according to the text record; computing a weighting value for each fragmentary creation with respect to the entire digital creation; computing a fragmentary price for each fragmentary creation based on the price and each weighting value; and storing the charging approach, the profit-sharing mode, multiple labeled fragmentary creations, each weighting value, and each fragmentary price to generate an online-executable smart contract.

Abstract: The present application describes a system in package which features no printed circuit board inside an encapsulation structure and comprises: a copper holder with a silicon layer at a top face; a plurality of dies mounted on the silicon layer and electrically connected to a plurality of data pins of the copper holder; a passive element mounted on the silicon layer and electrically connected to the dies wherein the dies are electrically connected to the ground pin of the copper holder; a molding compound encasing the dies and the passive element on the top face of the copper holder.

Abstract: The present application discloses a thinning system in package featuring an encapsulation structure in which no printed circuit board exists and comprising: a plurality of dies mounted on a top face of a copper holder and electrically connected to the plurality of data pins on the copper holder; a passive element mounted on the top face and electrically connected to the dies wherein the dies are electrically connected to the ground pin of the copper holder and both the dies and the passive element are fixed on the top face of the copper holder through a layer of insulation adhesives; a molding compound encasing the dies and the passive element on the top face of the copper holder.

Abstract: A method of measuring an azimuth of a target by a scanning radar includes (a) establishing a radar scanning model, including (a1) selecting an antenna pattern, (a2) setting a set of radar parameters, (a3) creating reflected signals simulation curve, (a4) sampling the reflected signals simulation curve to create a plurality of sets of simulation data, each set is consisted of successive samples, and (a5) normalizing each sample of each set of simulation data to create a plurality sets of records of normalized simulation data; (b) obtaining normalized scanning data; (c) comparing records of normalized simulation data with the normalized scanning data; and (d) obtaining an azimuth of the target.

Abstract: An abutment assembly includes an abutment, an adjustable buffer member and an adhesive. There is an angle between an extending direction of the abutment and a Z-axis direction, and the angle is greater than or equal to 0 degrees and smaller than or equal to 30 degrees. The adjustable buffer member is closely connected to the abutment having a positioning structure. The adjustable buffer member includes an engaging structure, an inner side wall, a base portion and a grinding portion. The engaging structure is engaged with the positioning structure. The inner side wall has at least one inner annular groove corresponding to the engaging structure. The base portion has a base thickness which is smaller than or equal to 4 mm. The adhesive is connected between the abutment and the adjustable buffer member, and contained in the inner annular groove. The grinding portion is manufactured by the instrument.

Abstract: The disclosure is related a method for testing a magnetic memory device and a test apparatus are provided. In some exemplary embodiments, the method includes at least the following steps. The magnetic memory device is initialized by applying a first magnetic field to force write a first data to the magnetic memory device. Then, a second magnetic field is applied to the magnetic memory device. Second data may be obtained from the magnetic memory device by performing a chip probing process. Accordingly, performance of the magnetic memory device may be determined based on the second data.

Abstract: A method of measuring an azimuth of a target by a scanning radar includes (a) establishing a radar scanning model, including (a1) selecting an antenna pattern, (a2) setting a set of radar parameters, (a3) creating reflected signals simulation curve, (a4) sampling the reflected signals simulation curve to create a plurality of sets of simulation data, each set is consisted of successive samples, and (a5) normalizing each sample of each set of simulation data to create a plurality sets of records of normalized simulation data; (b) obtaining normalized scanning data; (c) comparing records of normalized simulation data with the normalized scanning data; and (d) obtaining an azimuth of the target.

Abstract: Compounds for use in prevention and treatment of neurodegenerative disease and pain are disclosed. In one embodiment of the invention, the compound is selected from the group consisting of N6-[(3-halothien-2-yl)methyl]adenosine, N6-[(4-halothien-2-yl)methyl]adenosine, and N6-[(5-halothien-2-yl)methyl]adenosine. In another embodiment of the invention, the compound is selected from the group consisting of N6-[(2-bromothien-3-yl)methyl]adenosine, N6-[(4-bromothien-3-yl)methyl]adenosine, N6-[(5-bromothien-3-yl)methyl]adenosine N6-[(2-chlorothien-3-yl)methyl]adenosine, N6-[(4-chlorothien-3-yl)methyl]adenosine, and N6-[(5-chlorothien-3-yl)methyl]adenosine. Also disclosed are methods of making and using the same.

Abstract: A rectangular semiconductor package and a method manufacturing the same described in the present disclosure features no carrier installed on a die cut from a wafer. In an embodiment, a first die on a top surface of a conductive routing layer is electrically connected to the conductive routing layer through a plurality of first metal wires, a plurality of conductive balls is installed on a bottom surface of the conductive routing layer, and a molding compound is used to encase the first die on the conductive routing layer. In another embodiment, a second die is added in the above rectangular semiconductor package and encased in the molding compound, as is the first die. Alternatively, the molding compound is processed such that the second die encapsulated in a package is stacked on the molding compound and electrically connected to the conductive routing layer.

Abstract: The disclosure is related a method for testing a magnetic memory device and a test apparatus are provided. In some exemplary embodiments, the method includes at least the following steps. The magnetic memory device is initialized by applying a first magnetic field to force write a first data to the magnetic memory device. Then, a second magnetic field is applied to the magnetic memory device. Second data may be obtained from the magnetic memory device by performing a chip probing process. Accordingly, performance of the magnetic memory device may be determined based on the second data.

Abstract: A rectangular semiconductor package and a method manufacturing the same described in the present disclosure features no carrier installed on a die cut from a wafer. In an embodiment, a first die on a top surface of a conductive routing layer is electrically connected to the conductive routing layer through a plurality of first metal wires, a plurality of conductive balls is installed on a bottom surface of the conductive routing layer, and a molding compound is used to encase the first die on the conductive routing layer. In another embodiment, a second die is added in the above rectangular semiconductor package and encased in the molding compound, as is the first die. Alternatively, the molding compound is processed such that the second die encapsulated in a package is stacked on the molding compound and electrically connected to the conductive routing layer.