Patents by Inventor Chun-Yao Chen
Chun-Yao Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120139022Abstract: Embedded memories. The devices include a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer, and a plurality of capacitors. The substrate comprises transistors. The first dielectric layer, embedding first and second conductive plugs electrically connecting the transistors therein, overlies the substrate. The second dielectric layer, comprising a plurality of capacitor openings exposing the first conductive plugs, overlies the first dielectric layer. The capacitors comprise a plurality of bottom plates, respectively disposed in the capacitor openings, electrically connecting the first conductive plugs, a plurality of capacitor dielectric layers respectively overlying the bottom plates, and a top plate, comprising a top plate opening, overlying the capacitor dielectric layers. The top plate opening exposes the second dielectric layer, and the top plate is shared by the capacitors.Type: ApplicationFiled: February 9, 2012Publication date: June 7, 2012Inventors: Yi-Ching Lin, Chun-Yao Chen, Chen-Jong Wang, Shou-Gwo Wuu, Chung S. Wang, Chien-Hua Huang, Kun-Lung Chen, Ping Yang
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Patent number: 8148223Abstract: Embedded memories. The devices include a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer, and a plurality of capacitors. The substrate comprises transistors. The first dielectric layer, embedding first and second conductive plugs electrically connecting the transistors therein, overlies the substrate. The second dielectric layer, comprising a plurality of capacitor openings exposing the first conductive plugs, overlies the first dielectric layer. The capacitors comprise a plurality of bottom plates, respectively disposed in the capacitor openings, electrically connecting the first conductive plugs, a plurality of capacitor dielectric layers respectively overlying the bottom plates, and a top plate, comprising a top plate opening, overlying the capacitor dielectric layers. The top plate opening exposes the second dielectric layer, and the top plate is shared by the capacitors.Type: GrantFiled: May 22, 2006Date of Patent: April 3, 2012Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Ching Lin, Chun-Yao Chen, Chen-Jong Wang, Shou-Gwo Wuu, Chung S. Wang, Chien-Hua Huang, Kun-Lung Chen, Ping Yang
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Publication number: 20110268166Abstract: A channel information feedback method adapted in a receiving end of a multiuser multiple input multiple output (MU MIMO) system has following steps. A subspace matrix and a magnitude matrix related to a transmitting end of the MU MIMO system are obtained according to a channel matrix corresponding to the receiving end. A first quantization is performed on the subspace matrix to generate a quantized subspace matrix. A second quantization is performed on an auxiliary information matrix to generate a quantized auxiliary information matrix, where the auxiliary information matrix is corresponding to the magnitude matrix and a residual subspace matrix, and the residual subspace matrix includes residual subspace information after the first quantization is performed on the subspace matrix. The quantized subspace matrix and the quantized auxiliary information matrix are fed back to the transmitting end through an uplink channel.Type: ApplicationFiled: April 29, 2011Publication date: November 3, 2011Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Chun-Yao Chen, Hsuan-Jung Su
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Patent number: 7884408Abstract: One-transistor RAM technology compatible with a metal gate process fabricates a metal gate electrode formed of the same metal material as a top electrode of a MIM capacitor embedded isolation structure. A gate dielectric layer is formed of the same high-k dielectric material as a capacitor dielectric of the MIM capacitor embedded isolation structure.Type: GrantFiled: August 9, 2007Date of Patent: February 8, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Chi Tu, Kuo-Chyuan Tzeng, Chung-Yi Chen, Jian-Yu Shen, Chun-Yao Chen, Hsiang-Fan Lee
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Publication number: 20100224925Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate, an isolation structure formed in the semiconductor substrate, a conductive layer formed over the isolation structure, and a metal-insulator-metal (MIM) capacitor formed over the isolation structure. The MIM capacitor has a crown shape that includes a top electrode, a first bottom electrode, and a dielectric disposed between the top electrode and the first bottom electrode, the first bottom electrode extending at least to a top surface of the conductive layer.Type: ApplicationFiled: March 4, 2009Publication date: September 9, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuo-Cheng Ching, Kuo-Chi Tu, Chun-Yao Chen
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Patent number: 7382012Abstract: A memory device having improved sensing speed and reliability and a method of forming the same are provided. The memory device includes a first dielectric layer having a low k value over a semiconductor substrate, a second dielectric layer having a second k value over the first dielectric layer, and a capacitor formed in the second dielectric layer wherein the capacitor comprises a cup region at least partially filled by the third dielectric layer. The memory device further includes a third dielectric layer over the second dielectric layer and a bitline over the third dielectric layer. The bitline is electrically coupled to the capacitor. A void having great dimensions is preferably formed in the cup region of the capacitor.Type: GrantFiled: February 24, 2006Date of Patent: June 3, 2008Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Chi Tu, Chun-Yao Chen, Yi-Ching Lin
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Publication number: 20080122032Abstract: A semiconductor device. The semiconductor device includes a substrate having an array region and a decoupling region, a first dielectric layer overlying the substrate, a second dielectric layer overlying the first dielectric layer, a plurality of active components formed in the first dielectric layer within the array region, a first capacitor formed in the second dielectric layer within the array region, a second capacitor formed in the second dielectric layer within the decoupling region, and a first plug formed in the first dielectric layer within the array region electrically connecting the active component and the first capacitor. The invention also provides a method of fabricating the semiconductor device.Type: ApplicationFiled: August 16, 2006Publication date: May 29, 2008Inventors: Kuo-Chi Tu, Chun-Yao Chen
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Publication number: 20080073688Abstract: One-transistor RAM technology compatible with a metal gate process fabricates a metal gate electrode formed of the same metal material as a top electrode of a MIM capacitor embedded isolation structure. A gate dielectric layer is formed of the same high-k dielectric material as a capacitor dielectric of the MIM capacitor embedded isolation structure.Type: ApplicationFiled: August 9, 2007Publication date: March 27, 2008Inventors: Kuo-Chi Tu, Kuo-Chyuan Tzeng, Chung-Yi Chen, Jian-Yu Shen, Chun-Yao Chen, Hsiang-Fan Lee
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Publication number: 20080057660Abstract: A semiconductor device using a recessed step gate. An embodiment comprises a recessed region in a portion of the substrate, a transistor with one source/drain region located within the recessed region and one source/drain region located out of the recessed region, a storage device connected to the source/drain located out of the recessed region, and a bit line connected to the source/drain located within the recessed region.Type: ApplicationFiled: August 29, 2006Publication date: March 6, 2008Inventors: Kuo-Chi Tu, Jai-Hoon Sim, Chun-Yao Chen
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Publication number: 20070267674Abstract: Embedded memories. The devices include a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer, and a plurality of capacitors. The substrate comprises transistors. The first dielectric layer, embedding first and second conductive plugs electrically connecting the transistors therein, overlies the substrate. The second dielectric layer, comprising a plurality of capacitor openings exposing the first conductive plugs, overlies the first dielectric layer. The capacitors comprise a plurality of bottom plates, respectively disposed in the capacitor openings, electrically connecting the first conductive plugs, a plurality of capacitor dielectric layers respectively overlying the bottom plates, and a top plate, comprising a top plate opening, overlying the capacitor dielectric layers. The top plate opening exposes the second dielectric layer, and the top plate is shared by the capacitors.Type: ApplicationFiled: May 22, 2006Publication date: November 22, 2007Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Ching Lin, Chun-Yao Chen, Chen-Jong Wang, Shou-Gwo Wuu, Chung S. Wang, Chien-Hua Huang, Kun-Lung Chen, Ping Yang
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Patent number: 7282757Abstract: A metal-insulator-metal (MIM) capacitor structure and method of manufacturing thereof. A plurality of MIM capacitor patterns is formed in two or more insulating layers. The insulating layers may comprise a via layer and a metallization layer of a semiconductor device. A top portion of the top insulating layer is recessed in a region between at least two adjacent MIM capacitor patterns. When the top plate material of the MIM capacitors is deposited, the top plate material fills the recessed area of the top insulating layer between the adjacent MIM capacitor pattern, forming a connecting region that couples together the top plates of the adjacent MIM capacitors. A portion of the MIM capacitor bottom electrode may be formed in a first metallization layer of the semiconductor device.Type: GrantFiled: October 20, 2003Date of Patent: October 16, 2007Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Chi Tu, Chun-Yao Chen, Shou-Gwo Wuu, Chen-Jong Wang
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Patent number: 7271083Abstract: One-transistor RAM technology compatible with a metal gate process fabricates a metal gate electrode formed of the same metal material as a top electrode of a MIM capacitor embedded isolation structure. A gate dielectric layer is formed of the same high-k dielectric material as a capacitor dielectric of the MIM capacitor embedded isolation structure.Type: GrantFiled: July 22, 2004Date of Patent: September 18, 2007Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Chi Tu, Kuo-Chyuan Tzeng, Chung-Yi Chen, C. Y. Shen, Chun-Yao Chen, Hsiang-Fan Lee
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Patent number: 7268312Abstract: A button protecting structure is for an electronic product. The electronic product comprises a housing, a printed circuit board (PCB) installed in the housing, and a button module installed in the housing and touchable with the PCB to execute specific functions. The button module has a plurality of bridge sections in which one end of each bridge section is positioned in the housing. The button protecting structure comprises a connection unit and a stopping unit extended from the connection unit. The connection unit is detachably positioned in the housing and located at one side of the PCB. And, the stopping unit is extended and installed at a bottom of the PCB and positioned in a displacement path of each button. Whereby, a plurality of electronic elements or the PCB is prevented from being damaged and broken owing to an overdoing exerted force generated an accidental pressing on the button.Type: GrantFiled: September 16, 2005Date of Patent: September 11, 2007Assignee: Coretronic CorporationInventor: Chun-Yao Chen
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Publication number: 20070200162Abstract: A memory device having improved sensing speed and reliability and a method of forming the same are provided. The memory device includes a first dielectric layer having a low k value over a semiconductor substrate, a second dielectric layer having a second k value over the first dielectric layer, and a capacitor formed in the second dielectric layer wherein the capacitor comprises a cup region at least partially filled by the third dielectric layer. The memory device further includes a third dielectric layer over the second dielectric layer and a bitline over the third dielectric layer. The bitline is electrically coupled to the capacitor. A void having great dimensions is preferably formed in the cup region of the capacitor.Type: ApplicationFiled: February 24, 2006Publication date: August 30, 2007Inventors: Kuo-Chi Tu, Chun-Yao Chen, Yi-Ching Lin
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Publication number: 20070058334Abstract: An input/output device used for connecting at least one external wire with a display apparatus, comprises a case, at least one I/O connector, a flip cover, and a lighting device. The case embedded in the case of the display apparatus has a wiring slot to provide the wire passing through the case. The I/O connectors embedded on the case are electrically connected to the display apparatus. The flip cover is pivoted on the case. The lighting device having a light source and a switch is associated with the flip cover to turn on or turn off the light source.Type: ApplicationFiled: August 31, 2006Publication date: March 15, 2007Inventors: Chun-Yao Chen, Kuo-Chou Chang, Wei-Cheng Huang
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Patent number: 7148934Abstract: A rear projection television includes a casing with a space therein and a plurality of modular units. A plurality of maintenance holes are formed through the casing to communicate with the space. The modular units are positioned in the space to correspond to the maintenance holes. When one component inside the casing needs repairing, only a lid covering the corresponding maintenance hole is dismounted for the user to quickly take the component out, without moving the casing. Thereby, the repair process is simplified with saved repair labor and space.Type: GrantFiled: January 13, 2004Date of Patent: December 12, 2006Assignee: Coretronic CorporationInventors: Yi-Cheng Yuan, Chun-Yao Chen, Yung-Chuan Tseng, Chih-Chung Kang
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Patent number: 7115935Abstract: A method for fabricating a metal-insulator-metal capacitor in an embedded DRAM process is described. A plurality of contact plugs are provided through an insulating layer to semiconductor device structures in a substrate wherein the contact plugs are formed in a logic area of the substrate and in a memory area of the substrate and providing node contact plugs to node contact regions within the substrate in the memory area. Thereafter, capacitors are fabricated in a twisted trench in a self-aligned copper process.Type: GrantFiled: April 9, 2004Date of Patent: October 3, 2006Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kuo-Chi Tu, Chun-Yao Chen, Huey-Chi Chu
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Publication number: 20060084305Abstract: A button protecting structure is for an electronic product. The electronic product comprises a housing, a printed circuit board (PCB) installed in the housing, and a button module installed in the housing and touchable with the PCB to execute specific functions. The button module has a plurality of bridge sections in which one end of each bridge section is positioned in the housing. The button protecting structure comprises a connection unit and a stopping unit extended from the connection unit. The connection unit is detachably positioned in the housing and located at one side of the PCB. And, the stopping unit is extended and installed at a bottom of the PCB and positioned in a displacement path of each button. Whereby, a plurality of electronic elements or the PCB is prevented from being damaged and broken owing to an overdoing exerted force generated an accidental pressing on the button.Type: ApplicationFiled: September 16, 2005Publication date: April 20, 2006Applicant: Coretronic CorporationInventor: Chun-Yao Chen
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Publication number: 20060017115Abstract: One-transistor RAM technology compatible with a metal gate process fabricates a metal gate electrode formed of the same metal material as a top electrode of a MIM capacitor embedded isolation structure. A gate dielectric layer is formed of the same high-k dielectric material as a capacitor dielectric of the MIM capacitor embedded isolation structure.Type: ApplicationFiled: July 22, 2004Publication date: January 26, 2006Inventors: Kuo-Chi Tu, Kuo-Chyuan Tzeng, Chung-Yi Chen, C. Shen, Chun-Yao Chen, Hsiang-Fan Lee
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Publication number: 20050280981Abstract: The invention provides a modularized rotatable signal control box which is assembled in a housing of an electronic appliance. The signal control box comprises a module base and a rotatable module. The module base is assembled in the housing of the electronic appliance. The rotatable module comprises a hidden panel and at least one rotating element. The hidden panel comprises at least one signal input/output connector, and the rotating element is used for rotatably connecting the rotatable module to the module base.Type: ApplicationFiled: June 16, 2005Publication date: December 22, 2005Inventor: Chun-Yao Chen