Patents by Inventor Chun-Yi Yang

Chun-Yi Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6821684
    Abstract: A method for fabricating a Mask ROM with self-aligned coding is described. A plurality of buried bit lines are formed in a substrate, and then a plurality of word lines are formed on the substrate crossing over the buried bit lines with first blocking strips thereon. A plurality of second blocking strips are formed between the word lines and between the first blocking strips, and then the first blocking strips are patterned into an array of blocking bumps, which define a plurality of pre-coding windows with the second blocking strips. A coding mask layer is formed on the substrate with a plurality of coding windows therein exposing selected pre-coding windows, and then a coding implantation is performed to form implanted coding regions in the substrate under the selected pre-coding regions exposed by the coding windows. The coding mask layer is then removed.
    Type: Grant
    Filed: August 8, 2002
    Date of Patent: November 23, 2004
    Assignee: Macronix International Co., Ltd.
    Inventors: Chun-Yi Yang, Ta-Hung Yang
  • Publication number: 20040209458
    Abstract: The present invention discloses a semiconductor device having a rounding profile structure for reducing the step profile and the manufacturing processing stress and a method for rounding the corner of the membrane element in a semiconductor device. In the present invention, a membrane is deposited on a semiconductor substrate, then after a photo-resist pattern transferring step, dry etching step, and photo-resist removing step, a patterned membrane element is formed thereon. Then, a sacrificing layer is formed conformally overlaying the patterned membrane element, wherein the sacrificing layer is step height according to the patterned membrane element. Following, an etching back step is performed to etch the sacrificing layer by selectivity etching to form a rounding profile of the coroner of the membrane element. Last, the residual sacrificing layer is removed.
    Type: Application
    Filed: April 16, 2003
    Publication date: October 21, 2004
    Inventors: Shin Yi Tsai, Chun Yi Yang
  • Patent number: 6794253
    Abstract: A method of fabricating a mask ROM is provided, gate dielectric and a plurality of first conductive strips are sequentially formed over a substrate. A first dielectric layer is formed over the substrate and the first conductive strips. The first dielectric layer is patterned to form a plurality of first coding openings. Each first coding opening exposes the first conductive layer. A plurality of first wells is formed in the first conductive layer at the bottom of the first coding openings. A plurality of second conductive strips is formed over the first dielectric layer and inside the first coding openings to connect electrically with corresponding first wells and form a diode memory cell array. Additional diode memory cell arrays may stack over the diode memory cell array to increase device integration.
    Type: Grant
    Filed: February 24, 2003
    Date of Patent: September 21, 2004
    Assignee: Macronix International Co., Ltd.
    Inventors: Shang-Ping Lin, Tsung-Yi Chou, Chun-Yi Yang, Hsiang-Pang Lee
  • Publication number: 20040166639
    Abstract: A method of fabricating a mask ROM is provided. gate dielectric and a plurality of first conductive strips are sequentially formed over a substrate. A first dielectric layer is formed over the substrate and the first conductive strips. The first dielectric layer is patterned to form a plurality of first coding openings. Each first coding opening exposes the first conductive layer. A plurality of first wells is formed in the first conductive layer at the bottom of the first coding openings. A plurality of second conductive strips is formed over the first dielectric layer and inside the first coding openings to connect electrically with corresponding first wells and form a diode memory cell array. Additional diode memory cell arrays may stack over the diode memory cell array to increase device integration.
    Type: Application
    Filed: February 24, 2003
    Publication date: August 26, 2004
    Inventors: SHANG-PING LIN, TSUNG-YI CHOU, CHUN-YI YANG, HSIANG-PANG LEE
  • Publication number: 20040161896
    Abstract: A buried bit line and a fabrication method thereof, wherein the device includes a substrate, a shallow doped region disposed in the substrate, a deep doped region disposed in the substrate below a part of the shallow doped region, wherein the shallow doped region and the deep dope region together form a bit line of the memory device.
    Type: Application
    Filed: February 17, 2004
    Publication date: August 19, 2004
    Inventors: Jiun-Ren Lai, Chun-Yi Yang, Shi-Xian Chen, Gwen Chang
  • Patent number: 6720629
    Abstract: A buried bit line and a fabrication method thereof, wherein the device includes a substrate, a shallow doped region disposed in the substrate, a deep doped region disposed in the substrate below a part of the shallow doped region, wherein the shallow doped region and the deep dope region together form a bit line of the memory device.
    Type: Grant
    Filed: October 8, 2002
    Date of Patent: April 13, 2004
    Assignee: Macronix International Co., Ltd.
    Inventors: Jiun-Ren Lai, Chun-Yi Yang, Shi-Xian Chen, Gwen Chang
  • Publication number: 20040029049
    Abstract: A method for fabricating a Mask ROM with self-aligned coding is described. A plurality of buried bit lines are formed in a substrate, and then a plurality of word lines are formed on the substrate crossing over the buried bit lines with first blocking strips thereon. A plurality of second blocking strips are formed between the word lines and between the first blocking strips, and then the first blocking strips are patterned into an array of blocking bumps, which define a plurality of pre-coding windows with the second blocking strips. A coding mask layer is formed on the substrate with a plurality of coding windows therein exposing selected pre-coding windows, and then a coding implantation is performed to form implanted coding regions in the substrate under the selected pre-coding regions exposed by the coding windows. The coding mask layer is then removed.
    Type: Application
    Filed: August 8, 2002
    Publication date: February 12, 2004
    Inventors: Chun-Yi Yang, Ta-Hung Yang
  • Publication number: 20040004256
    Abstract: A buried bit line and a fabrication method thereof, wherein the device includes a substrate, a shallow doped region disposed in the substrate, a deep doped region disposed in the substrate below a part of the shallow doped region, wherein the shallow doped region and the deep dope region together form a bit line of the memory device.
    Type: Application
    Filed: October 8, 2002
    Publication date: January 8, 2004
    Inventors: Jiun-Ren Lai, Chun-Yi Yang, Shi-Xian Chen, Gwen Chang
  • Patent number: 6649526
    Abstract: A method for implanting and coding a read-only memory with automatic alignment at four corners includes the steps of: etching back the shielding layer on the spaced-striped first polysilicon layers; forming a spacing layer on the gate oxide layer and between the striped first polysilicon layers; depositing a second polysilicon layer overlying the spacing layer and the spaced-striped first polysilicon layer; exposing the gate oxide layer and etching the second polysilicon layer to become a plurality of striped second polysilicon layers; depositing an isolating layer on an etched portion of the striped first polysilicon layers and an etching portion of the striped second polysilicon layers; and using the striped second polysilicon layer as a mask, code areas are defined.
    Type: Grant
    Filed: November 15, 2001
    Date of Patent: November 18, 2003
    Assignee: Macronix International Co., Ltd.
    Inventor: Chun Yi Yang
  • Publication number: 20030198898
    Abstract: A method for fabricating a MOSFET structure having a source/drain extension and a source/drain region is disclosed, in which a basic antireflection coating is formed over a semiconductor substrate. A photoresist layer is formed over the basic antireflection coating. The photoresist layer is exposed to a radiation for transferring a pattern on the photoresist layer and the exposed photoresist layer is developed to form an opening over the areas for forming the source/drain regions, as a result a photoresist pattern with footing structures at a bottom comer of the photoresist pattern is formed. An ion implantation using the photoresist pattern as a mask, to simultaneously to form a source/drain extension and a source/drain region.
    Type: Application
    Filed: April 17, 2002
    Publication date: October 23, 2003
    Inventors: Shun-Li Lin, Chun-Yi Yang
  • Publication number: 20030092275
    Abstract: A method for implanting and coding a read-only memory with automatic alignment at four corners for being used in a mask memory is disclosed. The method comprises the steps of: etching back the shielding layer on the spaced-striped first polysilicon layers; forming a spacing layer on the gate oxide layer and between the striped first polysilicon layers; depositing a second polysilicon layer overlying the spacing layer and the spaced-striped first polysilicon layer; etching the second polysilicon layer and the spaced-striped first polysilicon layers to expose the gate oxide layer and the second polysilicon layer becomes a plurality of striped second polysilicon layers; depositing an isolating layer on an etching portion of the striped first polysilicon layers and an etching portion of the striped second polysilicon layers; and using the striped second polysilicon layer as a mask and defining code areas for performing the process of implantation and coding.
    Type: Application
    Filed: November 15, 2001
    Publication date: May 15, 2003
    Inventor: Chun Yi Yang
  • Publication number: 20020168822
    Abstract: A method of fabricating a mask read only memory. Gate stacked structures, each of which made up of a gate dielectric layer, a gate conductive layer and a gate cap layer, are formed on a substrate. Source/drain regions are between, but not adjacent to the gate stacked structures. Regions between the source/drain regions and the gate stacked structures are coding areas. A dielectric layer is formed to fill spaces between the gate stacked structures. A photoresist layer with openings exposing the first dielectric layer on the coding areas is formed. The exposed first dielectric layer is removed to form implantation openings of the coding areas. Ion implantation is performed on the exposed coding areas. The photoresist layer is removed, and another dielectric layer is formed to fill the implantation openings. An etching back process is performed to expose the gate conductive layer. A word line is formed on the gate conductive layer.
    Type: Application
    Filed: August 14, 2001
    Publication date: November 14, 2002
    Inventors: Chun-Yi Yang, Chun-Jung Lin, Ful-Long Ni
  • Patent number: 6468869
    Abstract: A method of fabricating a mask read only memory. Gate stacked structures, each of which made up of a gate dielectric layer, a gate conductive layer and a gate cap layer, are formed on a substrate. Source/drain regions are between, but not adjacent to the gate stacked structures. Regions between the source/drain regions and the gate stacked structures are coding areas. A dielectric layer is formed to fill spaces between the gate stacked structures. A photoresist layer with openings exposing the first dielectric layer on the coding areas is formed. The exposed first dielectric layer is removed to form implantation openings of the coding areas. Ion implantation is performed on the exposed coding areas. The photoresist layer is removed, and another dielectric layer is formed to fill the implantation openings. An etching back process is performed to expose the gate conductive layer. A word line is formed on the gate conductive layer.
    Type: Grant
    Filed: August 14, 2001
    Date of Patent: October 22, 2002
    Assignee: Macronix International Co., Ltd.
    Inventors: Chun-Yi Yang, Chun-Jung Lin, Ful-Long Ni
  • Patent number: 6440803
    Abstract: A method of fabricating a mask ROM, in which conductive strips are formed with a cap layer on each of them, then a plurality of spacers are formed on the side-walls of the conductive strips, while the substrate under the spacers are used as the coding regions. The buried bit-lines are formed in the substrate between the spacers, then a two-step coding process is performed, wherein the coding regions at the first and the second side of the conductive strips are selectively doped by a first and a second tilt coding implantation with a first and a second coding mask. After the second mask layer and the cap layer are removed, a conductive layer is formed over the substrate, then the conductive layer and the conductive strips are patterned successively to form a plurality of word-lines and plural gates, respectively.
    Type: Grant
    Filed: January 14, 2002
    Date of Patent: August 27, 2002
    Assignee: Macronix International Co., LTD
    Inventors: Shui-Chin Huang, Yen-hung Yeh, Tso-Hung Fan, Chun-Yi Yang, Chun-Jung Lin
  • Patent number: 6397377
    Abstract: The present invention provides a method of performing optical proximity corrections of a photo mask pattern by using a computer. The photo mask pattern is formed on a photo mask which is used when performing photolithography for forming a predetermined original pattern by exposing a photo-resist layer in a predetermined area of a semiconductor wafer. The photo mask pattern is divided into a plurality of rectangular blocks. Each block can be bright or dark, and a least one side and two corners of the block are shared with another block. Each of shared corners is checked to find corners which may be affected by an optic proximity effect, and those corners are modified so as to prevent them from being affected by the optic proximity effect.
    Type: Grant
    Filed: October 8, 1999
    Date of Patent: May 28, 2002
    Assignee: Macronix International Co. Ltd.
    Inventors: Bing-Ying Wang, Chun-Yi Yang, Chun-Jung Lin, Jui-Chin Chang, Mam-Tsung Wang
  • Patent number: 6166943
    Abstract: The present invention provides a method of writing a set of binary codes into a ROM. The method is performed by forming a first photo mask and a second photo mask according to an original first code pattern, an original second code pattern, and a set of binary codes to be written into the ROM. Final first and second code patterns are formed by coupling the binary codes to be written with the original first and second code patterns by using a Boolean logical OR operation. The first and second photo masks are formed according to the final first and second code patterns. The first photolithographic process is performed using the first photo mask, and the first ion implantation process is performed; the second photolithographic process is performed using the second photo mask, and the second ion implantation process is performed. Thus the set of binary codes is written into the ROM completely and correctly.
    Type: Grant
    Filed: October 20, 1999
    Date of Patent: December 26, 2000
    Assignee: Macronix International Co, Ltd
    Inventors: Ping-Ying Wang, Chun-Yi Yang, Chun-Jung Lin, Jui-Chin Chang, Mam-Tsung Wang