Patents by Inventor Chung Chang

Chung Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230387213
    Abstract: A semiconductor structure includes a SiGe fin protruding from a substrate, where the SiGe fin includes a top portion having a first sidewall and a second sidewall and a bottom portion having a third sidewall and a fourth sidewall, and where a first transition region connecting the first sidewall to the third sidewall and a second transition region connecting the second sidewall to the fourth sidewall each have a tapered profile extending away from the first sidewall and the second sidewall, respectively, and a Si-containing layer disposed on the top portion of the SiGe fin, where a portion of the Si-containing layer on the first transition region extends away from the first sidewall by a first lateral distance and a portion of the Si-containing layer on the second transition region extends away from the second sidewall by a second lateral distance that is different from the first lateral distance.
    Type: Application
    Filed: August 9, 2023
    Publication date: November 30, 2023
    Inventors: Yu-Shan Lu, Hung-Ju Chou, Pei-Ling Gao, Chen-Hsuan Liao, Chih-Chung Chang, Jiun-Ming Kuo, Che-Yuan Hsu
  • Patent number: 11829001
    Abstract: An optical system is provided. The optical system includes an immovable part, a second movable part, a second drive mechanism, and a second circuit mechanism. The second movable part is used for connecting to a second optical element. The second movable part is movable relative to the immovable part. The second drive mechanism is used for driving the second movable part to move relative to the immovable part. The second circuit mechanism is electrically connected to the second drive mechanism.
    Type: Grant
    Filed: January 22, 2021
    Date of Patent: November 28, 2023
    Assignee: TDK TAIWAN CORP.
    Inventors: Chan-Jung Hsu, I-Mei Huang, Yi-Ho Chen, Shao-Chung Chang, Ichitai Moto, Chen-Chi Kuo, Ying-Jen Wang, Ya-Hsiu Wu, Wei-Jhe Shen, Chao-Chang Hu, Che-Wei Chang, Sin-Jhong Song, Shu-Shan Chen, Chih-Wei Weng, Chao-Hsi Wang
  • Patent number: 11823981
    Abstract: A semiconductor package includes a substrate, a composite seed-barrier layer, a routing via, and a semiconductor die. The substrate has a through hole formed therethrough. The composite seed-barrier layer extends on sidewalls of the through hole and includes a first barrier layer, a seed layer, and a second barrier layer sequentially stacked on the sidewalls of the through hole. The routing via fills the through hole and is separated from the substrate by the composite seed-barrier layer. The semiconductor die is electrically connected to the routing via. Along the sidewalls of the through holes, at a level height corresponding to half of a total thickness of the substrate, the seed layer is present as inclusions of seed material surrounded by barrier material of the first barrier layer and the second barrier layer.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: November 21, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Chung Chang, Ming-Che Ho, Hung-Jui Kuo
  • Publication number: 20230366739
    Abstract: An infrared device is provided. The infrared device includes a substrate, a metal layer, a first semiconductor layer, an absorber layer, and a second semiconductor layer. The metal layer is disposed on the substrate. The first semiconductor layer is disposed on the substrate and electrically connected to the metal layer. A cavity is formed between the first semiconductor layer and the metal layer. The absorber layer is disposed on the first semiconductor layer. The second semiconductor layer is disposed on the absorber layer and electrically connected to the first semiconductor layer. The TCR of the first semiconductor layer is different from that of the second semiconductor layer.
    Type: Application
    Filed: November 24, 2022
    Publication date: November 16, 2023
    Inventors: Heng-Chung CHANG, Chih-Ya Tsai, Hui-Chi Su, Jing-Yuan Lin
  • Patent number: 11817049
    Abstract: A display panel and a spliced display are provided. The display panel includes a substrate, a plurality of light-emitting elements, a driving circuit, and an optical sensor. The substrate includes a through hole, and the through hole includes a hole. The plurality of the light-emitting elements are disposed on the substrate. The through hole is located in a region between two of the plurality of the light-emitting elements. The driving circuit is disposed on the substrate and electrically connected to the plurality of the light-emitting elements. The optical sensor is disposed corresponding to the through hole and receives sensing light through the hole. The width W of the hole meets the equation of H?W<D. H is the depth of the hole, and D is the distance between the two of the plurality of the light-emitting elements.
    Type: Grant
    Filed: October 7, 2022
    Date of Patent: November 14, 2023
    Assignee: Innolux Corporation
    Inventors: Chin-Lung Ting, Chien-Chih Chen, Ti Chung Chang, Chih-Chieh Wang, Jenhung Li
  • Patent number: 11808136
    Abstract: A method for evaluating a sealing material positioned between a casing of a wellbore and a subsurface formation in which the wellbore is formed includes emitting an acoustic waveform outward from a position within the casing and detecting a return waveform that is generated in response to the acoustic waveform interacting with a region of interest that includes at least a portion of the sealing material. The method includes determining a first time window of the return waveform associated with the region of interest and trimming the return waveform based on the first time window. The method further includes determining a first spectral power density for the first time window of the trimmed return waveform and determining a composition ratio for the region of interest based on the first spectral power density.
    Type: Grant
    Filed: May 27, 2021
    Date of Patent: November 7, 2023
    Assignee: Halliburton Energy Services, Inc.
    Inventors: Pablo Vieira Rego, Randolph S. Coles, Jeffrey James Crawford, Chung Chang
  • Publication number: 20230341654
    Abstract: An optical system includes an optical module with a main axis is provided. The optical module includes a fixed portion, a movable portion, and a driving mechanism. The movable portion is connected to an optical element and is movable relative to the fixed portion. The driving mechanism drives the movable portion to move relative to the fixed portion. When viewed along a direction that is parallel with the main axis, the fixed portion is a polygonal structure with a first side, a second side, a third side, and a fourth side. The first side is parallel with the third side, the second side is parallel with the fourth side, and the first side is not parallel with the second side.
    Type: Application
    Filed: June 29, 2023
    Publication date: October 26, 2023
    Inventors: Chan-Jung HSU, I-Mei HUANG, Yi-Ho CHEN, Shao-Chung CHANG, Ichitai MOTO, Chen-Chi KUO, Ying-Jen WANG, Ya-Hsiu WU, Wei-Jhe SHEN, Chao-Chang HU, Che-Wei CHANG, Sin-Jhong SONG, Shu-Shan CHEN, Chih-Wei WENG, Chao-Hsi WANG
  • Publication number: 20230341653
    Abstract: An optical system includes an optical module with a main axis is provided. The optical module includes a fixed portion, a movable portion, a driving mechanism, and a supporting assembly. The movable portion is connected to an optical element and is movable relative to the fixed portion. The driving mechanism drives the movable portion to move relative to the fixed portion. The supporting assembly is connected to the movable portion and the fixed portion. When viewed along a direction that is parallel with the main axis, the fixing portion is a polygonal structure with a first side, a second side, a third side, and a fourth side. The first side is parallel with the third side, the second side is parallel with the fourth side, and the first side is not parallel with the second side.
    Type: Application
    Filed: June 29, 2023
    Publication date: October 26, 2023
    Inventors: Chan-Jung HSU, I-Mei HUANG, Yi-Ho CHEN, Shao-Chung CHANG, Ichitai MOTO, Chen-Chi KUO, Ying-Jen WANG, Ya-Hsiu WU, Wei-Jhe SHEN, Chao-Chang HU, Che-Wei CHANG, Sin-Jhong SONG, Shu-Shan CHEN, Chih-Wei WENG, Chao-Hsi WANG
  • Patent number: 11791336
    Abstract: Semiconductor devices and methods of forming the same are provided. In an embodiment, a semiconductor device includes a first fin extending along a first direction, a second fin extending parallel to the first fin, and a gate structure over and wrapping around the first fin and the second fin, the gate structure extending along a second direction perpendicular to the first direction. The first fin bents away from the second fin along the second direction and the second fin bents away from the first fin along the second direction.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: October 17, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jiun-Ming Kuo, Pei-Ling Gao, Chen-Hsuan Liao, Hung-Ju Chou, Chih-Chung Chang, Che-Yuan Hsu
  • Publication number: 20230326890
    Abstract: Various embodiments of the present disclosure are directed towards a three-dimensional (3D) IC comprising semiconductor substrates with different bandgaps. The 3D IC chip comprises a first IC chip and a second IC chip overlying and bonded to the first IC chip. The first IC chip comprises a first semiconductor substrate with a first bandgap, and further comprises and a first device on and partially formed by the first semiconductor substrate. The second IC chip comprises a second semiconductor substrate with a second bandgap different than the first bandgap, and further comprises a second device on the second semiconductor substrate.
    Type: Application
    Filed: June 24, 2022
    Publication date: October 12, 2023
    Inventors: Yao-Chung Chang, Shih-Chien Liu, Chia-Jui Yu, Chun-Lin Tsai
  • Publication number: 20230327692
    Abstract: A chip comprises a plurality of signal receiving circuits, a transceiver circuit and a memory circuit. The plurality of signal receiving circuits are set at different locations on the chip. The transceiver circuit includes a dynamic switch circuit and a baseband processor. The dynamic switch circuit is configured to output a to-be-analyzed signal from the one of the plurality of signal receiving circuits. The baseband processor is configured to obtain a frequency spectrum and magnitude of the to-be-analyzed signal, and obtain a data packet of an input radio-frequency signal received by an external antenna. The memory circuit is configured to store the frequency spectrum and magnitude of the to-be-analyzed signal, and transmit the frequency spectrum and magnitude to an external computing device, so as to determine an interference path, an interference source or a combination thereof of an interference signal of the transceiver circuit through the external computing device.
    Type: Application
    Filed: October 16, 2022
    Publication date: October 12, 2023
    Inventor: Chung Chang LIN
  • Publication number: 20230326896
    Abstract: A COF package includes a substrate and a chip, composite bumps on the chip are bonded to leads on the substrate. Each of the composite bumps includes a raising strip, a UBM layer and a bonding layer. A bonding rib is formed on the bonding layer because of the raising strip and the UBM layer, and the bonding rib on each of the composite bumps can be inserted into each of the leads and surface-contact with each of the leads to increase weld length and bonding strength between the bonding layer and the leads and further reduce a force required for bonding the chip to the substrate in a flip-chip bonding process.
    Type: Application
    Filed: February 13, 2023
    Publication date: October 12, 2023
    Inventors: Sheng-Jen Wu, Shih-Chung Chang, Hsueh-Shun Yeh, Chun-Te Lee
  • Patent number: 11784900
    Abstract: An example method for using wireless packets to indicate boot status of a network device is disclosed. The method includes initiating a boot sequence of a network device. The method also includes during at least a portion of the boot sequence, transmitting a first wireless packet comprising data indicating a boot status of the network device, wherein the boot status indicates the network device is booting. The method also includes transmitting a second wireless packet comprising data indicating the boot status of the network device, wherein the boot status indicates the network device has finished booting.
    Type: Grant
    Filed: October 28, 2021
    Date of Patent: October 10, 2023
    Assignee: Ubiquiti Inc.
    Inventors: Robert J. Pera, Yao-Chung Chang, Andrejs Bogdanovs
  • Publication number: 20230310883
    Abstract: A shell of the present invention includes a light exiting surface with an opening; a power button is mounted on the shell; inside the shell, a proximity sensing module is mounted facing the light exiting surface, and a processing module is electrically connected to the proximity sensing module, the power switch, and a light emission module; when the power switch is switched on, the processing module enters a hibernation mode; when the processing module in hibernation mode receives a trigger signal sent by the proximity sensing module for sensing a human body in close proximity, the processing module exits the hibernation mode and controls the light emission module to generate a light therapy beam; the present invention ensures the opening is closely contacting the human body before generating the light therapy beam, decreasing risks of the light therapy beam exiting the opening and hitting human eyes directly.
    Type: Application
    Filed: April 1, 2022
    Publication date: October 5, 2023
    Inventors: Tsung-Jui LIN, Chen-Chung CHANG, Shuo-Ting YAN
  • Patent number: 11770975
    Abstract: Methods, systems and devices are disclosed for controlling self-induced acoustic interference. In one embodiment, a first piezoelectric transducer to which a first excitation signal is applied, generates back side acoustic waves that are transmitted from a back side of the first piezoelectric transducer into a backing material layer. A second piezoelectric transducer coupled to a back side of the backing material layer generates a first calibration response to the back side acoustic waves. An interference signal profile is generated based, at least in part, on the first calibration response and may be used to filter interference signal components and/or to generate a control signal to be applied to the second piezoelectric transducer during measurement cycles.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: September 26, 2023
    Assignee: Halliburton Energy Services, Inc.
    Inventors: Chung Chang, Jing Jin, Richard Timothy Coates
  • Publication number: 20230290841
    Abstract: Spacer self-aligned via structures for gate contact or trench contact are described. In an example, an integrated circuit structure includes a plurality of gate structures above a substrate. A plurality of conductive trench contact structures is alternating with the plurality of gate structures. A corresponding one of a plurality of dielectric spacers is between adjacent ones of the plurality of gate structures and the plurality of conductive trench contact structures. The plurality of dielectric spacers protrudes above the plurality of gate structures and above the plurality of conductive trench contact structures. A conductive structure is in direct contact with one of the plurality of gate structures or with one of the plurality of conductive trench contact structures. The conductive structure has a flat edge along a direction across the one of the plurality of gate structures or the one of the plurality of conductive trench contact structures.
    Type: Application
    Filed: March 11, 2022
    Publication date: September 14, 2023
    Inventors: Leonard P. GULER, Tsuan-Chung CHANG, Charles H. WALLACE, Tahir GHANI, Desalegne B. TEWELDEBRHAN
  • Publication number: 20230290825
    Abstract: Integrated circuit structures having backside self-aligned conductive source or drain contacts, and methods of fabricating integrated circuit structures having backside self-aligned conductive source or drain contacts, are described. For example, an integrated circuit structure includes a sub-fin structure over a vertical stack of horizontal nanowires. An epitaxial source or drain structure is laterally adjacent and coupled to the vertical stack of horizontal nanowires. A conductive source or drain contact is laterally adjacent to the sub-fin structure and is on and in contact with the epitaxial source or drain structure. The conductive source or drain contact does not extend around the epitaxial source or drain structure.
    Type: Application
    Filed: March 11, 2022
    Publication date: September 14, 2023
    Inventors: Leonard P. Guler, Sean Pursel, Raghuram Gandikota, Sikandar Abbas, Tsuan-Chung Chang, Mauro J. Kobrinsky, Tahir Ghani, Elliot N. Tan
  • Publication number: 20230280489
    Abstract: An acoustic logging tool may comprise a center load carrying pipe, a receiver module connected to the center load carrying pipe, one or more transmitter modules connected to the center load carrying pipe, and one or more mass modules connected to the center load carrying pipe.
    Type: Application
    Filed: May 11, 2023
    Publication date: September 7, 2023
    Applicant: Halliburton Energy Services, Inc.
    Inventors: Chung Chang, Qingtao Sun, Randolph S. Coles, Federico Lucas, Jr.
  • Publication number: 20230282723
    Abstract: A method for forming a semiconductor device structure is provided. The semiconductor device structure includes a first fin structure formed over a substrate, and the first fin structure includes a plurality of first nanostructures stacked in a vertical direction. The semiconductor device structure further includes a second fin structure formed over the substrate, and the second fin structure includes a plurality of second nanostructures stacked in a vertical direction. The semiconductor device structure further includes a dummy fin structure between the first fin structure and the second fin structure. The dummy fin structure includes a first etching stop layer between a bottom portion and a top portion.
    Type: Application
    Filed: March 2, 2022
    Publication date: September 7, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Shao LIN, Yi-Hsiu LIU, Chih-Chung CHANG, Chung-Ting KO, Sung-En LIN
  • Publication number: 20230282724
    Abstract: Techniques are provided herein to form an integrated circuit having gate cut structures or plug structures between source or drain regions, with an angled cut made to the top portion of the structures. In an example, a semiconductor device includes a semiconductor region extending between source and drain regions, and a gate structure extending over the semiconductor region. A gate cut structure is present adjacent to the semiconductor device and interrupts the gate structure. The gate cut structure has a first width along a first plane that extends through the semiconductor region and a second width along a second plane parallel to the first plane and above the semiconductor region, where the first width is greater than the second width. Similar angled plug structures may be provided adjacent to the source and drain regions to increase the landing area made to the metal contacts on the source and drain regions.
    Type: Application
    Filed: March 4, 2022
    Publication date: September 7, 2023
    Applicant: Intel Corporation
    Inventors: Leonard P. Guler, Tsuan-Chung Chang, Charles H. Wallace, Peter P. Sun, Tahir Ghani, Virupaxi Goornavar