Patents by Inventor Chung-Fu Chang

Chung-Fu Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9724842
    Abstract: A method of making a buffer board of a treadmill includes a sizing step, a shade drying step, a presetting step, a clamping and heat-pressing step, a cooling step, and a die opening step. The method can easily make the desired buffer board adapted to the treadmill and can only change different dies to make buffer boards with different structures when an upper die and a lower die of a die set provide protrusions, flat surfaces or depressed surfaces, thereby reducing the manufacturing cost.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: August 8, 2017
    Inventor: Chung-Fu Chang
  • Patent number: 9691901
    Abstract: A semiconductor device includes a substrate, a gate structure, a sidewall spacer, and an epitaxial layer. The gate structure is disposed on the substrate, and the substrate has at least one recess disposed adjacent to the gate structure. The sidewall spacer is disposed on at least two sides of the gate structure. The sidewall spacer includes a first spacer layer and a second spacer layer, and the first spacer layer is disposed between the gate structure and the second spacer layer. The epitaxial layer is disposed in the recess, and the recess is a circular shaped recess. A distance between an upmost part of the recess and the gate structure is less than a width of the sidewall spacer.
    Type: Grant
    Filed: October 2, 2015
    Date of Patent: June 27, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wen-Jiun Shen, Chia-Jong Liu, Chung-Fu Chang, Yen-Liang Wu, Man-Ling Lu, I-Fan Chang, Yi-Wei Chen
  • Patent number: 9666715
    Abstract: A field effect transistor with epitaxial structures includes a fin-shaped structure and a metal gate across the fin-shaped structure. The metal gate includes a pair of recess regions disposed on two sides of the bottom of the metal gate.
    Type: Grant
    Filed: January 19, 2015
    Date of Patent: May 30, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chung-Fu Chang, Chun-Hsien Lin, Chen-Yi Weng
  • Patent number: 9634125
    Abstract: A field effect transistor (FinFET) device includes a substrate, a fin structure, a shallow trench isolation and a gate structure. The fin structure is formed on a surface of the substrate and includes a base fin structure and an epitaxial fin structure formed on the base fin structure. The shallow trench isolation structure is formed on the surface of the substrate and includes a peripheral zone and a concave zone. The peripheral zone physically contacts with the fin structure. The gate structure is disposed on the epitaxial fin structure perpendicularly. A method of fabricating the aforementioned field effect transistor is also provided.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: April 25, 2017
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Yen-Liang Wu, Chung-Fu Chang, Yu-Hsiang Hung, Ssu-I Fu, Wen-Jiun Shen, Man-Ling Lu, Chia-Jong Liu, Yi-Wei Chen
  • Publication number: 20170098708
    Abstract: A semiconductor device includes a substrate, a gate structure, a sidewall spacer, and an epitaxial layer. The gate structure is disposed on the substrate, and the substrate has at least one recess disposed adjacent to the gate structure. The sidewall spacer is disposed on at least two sides of the gate structure. The sidewall spacer includes a first spacer layer and a second spacer layer, and the first spacer layer is disposed between the gate structure and the second spacer layer. The epitaxial layer is disposed in the recess, and the recess is a circular shaped recess. A distance between an upmost part of the recess and the gate structure is less than a width of the sidewall spacer.
    Type: Application
    Filed: October 2, 2015
    Publication date: April 6, 2017
    Inventors: Wen-Jiun Shen, Chia-Jong Liu, Chung-Fu Chang, Yen-Liang Wu, Man-Ling Lu, I-Fan Chang, Yi-Wei Chen
  • Publication number: 20170087398
    Abstract: A fitness auxiliary device includes first and second support boards, a holding rod, a top rod, a pull rod, a caster seat, a buckle member, and casters. The top rod is transversely disposed at upper ends of inclined surfaces of the first and second support boards. The holding rod is located under the top rod. The pull rod is transversely disposed at the lower ends of the inclined surfaces and located under the holding rod. The caster seat is fixedly connected to the middle of the pull rod. A front end of the caster seat is provided with the buckle member. Two ends of an elastic rope are provided with buckle heads for connecting the buckle hole and a slide board or a flat board, such that the fitness auxiliary device can be used variously.
    Type: Application
    Filed: September 25, 2015
    Publication date: March 30, 2017
    Inventor: Chung-Fu Chang
  • Patent number: 9601600
    Abstract: A process for fabricating a fin-type field effect transistor (FinFET) structure is described. A semiconductor substrate is patterned to form a fin. A spacer is formed on the sidewall of the fin. A portion of the fin is removed, such that the spacer and the surface of the remaining fin together define a cavity. A piece of a semiconductor compound is formed from the cavity, wherein the upper portion of the piece of the semiconductor compound laterally extends over the spacer.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: March 21, 2017
    Assignee: United Microelectronics Corp.
    Inventors: Yu-Hsiang Hung, Ssu-I Fu, Chung-Fu Chang, Yen-Liang Wu, Cho-Han Fan, Chien-Ting Lin
  • Publication number: 20170072586
    Abstract: A method of making a buffer board of a treadmill includes a sizing step, a shade drying step, a presetting step, a clamping and heat-pressing step, a cooling step, and a die opening step. The method can easily make the desired buffer board adapted to the treadmill and can only change different dies to make buffer boards with different structures when an upper die and a lower die of a die set provide protrusions, flat surfaces or depressed surfaces, thereby reducing the manufacturing cost.
    Type: Application
    Filed: September 14, 2015
    Publication date: March 16, 2017
    Inventor: Chung-Fu Chang
  • Patent number: 9573017
    Abstract: A buffer board structure of a treadmill includes bamboo layers made by attaching bamboo sheets side by side, a bottom surface of which is adhered by a membrane layer whereby the bamboo sheets are firmly stuck on the membrane layer. Each membrane layer has an upper and lower faces respectively stuck between the bamboo layers. The bamboo sheets of each bamboo layer face the same juxtaposing direction, whereas bamboo layers juxtaposed lengthways provide a better buffer. By setting one membrane layer between two bamboo layers, contact faces of the bamboo layers and the membrane layer adhered together become smoother, and an adhesive fills in a gap more evenly. A slip resistant layer is stuck on the top bamboo layer. A smoother buffering effect and a stable juxtaposition are obtained when the bamboo layers are trodden to prevent the breakdown of buffer relations between the bamboo sheets and the membrane layers.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: February 21, 2017
    Inventor: Chung-Fu Chang
  • Patent number: 9502530
    Abstract: A method of manufacturing a semiconductor device including the steps of providing a substrate having first type semiconductor regions and second type semiconductor regions, forming a conformal first epitaxy mask layer on the substrate, forming first type epitaxial layer in the substrate of the first type semiconductor regions, forming a conformal second epitaxy mask layer on the substrate, forming second type epitaxial layer in the substrate of the second type semiconductor regions, and removing the second epitaxy mask layer.
    Type: Grant
    Filed: November 8, 2015
    Date of Patent: November 22, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Hsiang Hung, Chung-Fu Chang, Chia-Jong Liu, Yen-Liang Wu, Pei-Yu Chou, Home-Been Cheng
  • Publication number: 20160260820
    Abstract: An etching method adapted to forming grooves in Si-substrate and FinFET transistor manufactured thereof are provided. The etching method includes providing a silicon substrate, at least two gate structures formed on the silicon substrate and at least two gate spacer structures disposed on the silicon substrate; performing a first etching process on the silicon substrate to form a first groove, which has a base and two inclined sidewalls, ascending to respective bottoms of the gate structures, and are interconnected with the base, respectively; and performing a second etching process on the silicon substrate at the base of the first groove, so as to form a second groove in a trench shape, wherein the two inclined sidewalls of the first groove are interconnected with the second groove respectively, and the first etching process is substantially different from the second etching process.
    Type: Application
    Filed: May 17, 2016
    Publication date: September 8, 2016
    Applicant: UNITED MICROELECTRONICS CORPORATION
    Inventors: JHEN-CYUAN LI, SHUI-YEN LU, MAN-LING LU, YU-CHENG TUNG, CHUNG-FU CHANG
  • Patent number: 9397190
    Abstract: A fabrication method of a semiconductor structure includes the following steps. First of all, a gate structure is provided on a substrate, and a first material layer is formed on the substrate and the gate structure. Next, boron dopant is implanted to the substrate, at two sides of the gate structure, to form a first doped region, and P type conductive dopant is implanted to the substrate, at the two sides of the gate structure, to form a second doped region. As following, a second material layer is formed on the first material layer. Finally, the second material layer, the first material layer and the substrate at the two sides of the gate structure are etched sequentially, and a recess is formed in the substrate, at the two sides of the gate structure, wherein the recess is positioned within the first doped region.
    Type: Grant
    Filed: July 27, 2014
    Date of Patent: July 19, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yen-Liang Wu, Chung-Fu Chang, Yu-Hsiang Hung, Ssu-I Fu, Man-Ling Lu, Chia-Jong Liu, Wen-Jiun Shen, Yi-Wei Chen
  • Patent number: 9385191
    Abstract: A FINFET structure is provided. The FINFET structure includes a substrate, a PMOS element, a NMOS element, a STI structure, and a bump structure. The substrate includes a first area and a second area adjacent to the first area. The PMOS element is disposed in the first area of the substrate, and includes at least one first fin structure. The NMOS element is disposed in the second area of the substrate and includes at least one second fin structure. The STI structure is disposed between the first fin structure and the second fin structure. The bump structure is disposed on the STI structure and has a carbon-containing dielectric material.
    Type: Grant
    Filed: November 20, 2014
    Date of Patent: July 5, 2016
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Yen-Liang Wu, Chung-Fu Chang, Wen-Jiun Shen, Man-Ling Lu, Chia-Jong Liu, Yi-Wei Chen
  • Publication number: 20160184625
    Abstract: A buffer board structure of a treadmill includes bamboo layers made by attaching bamboo sheets side by side, a bottom surface of which is adhered by a membrane layer whereby the bamboo sheets are firmly stuck on the membrane layer. Each membrane layer has an upper and lower faces respectively stuck between the bamboo layers. The bamboo sheets of each bamboo layer face the same juxtaposing direction, whereas bamboo layers juxtaposed lengthways provide a better buffer. By setting one membrane layer between two bamboo layers, contact faces of the bamboo layers and the membrane layer adhered together become smoother, and an adhesive fills in a gap more evenly. A slip resistant layer is stuck on the top bamboo layer. A smoother buffering effect and a stable juxtaposition are obtained when the bamboo layers are trodden to prevent the breakdown of buffer relations between the bamboo sheets and the membrane layers.
    Type: Application
    Filed: July 30, 2015
    Publication date: June 30, 2016
    Inventor: Chung-Fu Chang
  • Patent number: 9373718
    Abstract: An etching method adapted to forming grooves in Si-substrate and FinFET transistor manufactured thereof are provided. The etching method includes providing a silicon substrate, at least two gate structures formed on the silicon substrate and at least two gate spacer structures disposed on the silicon substrate; performing a first etching process on the silicon substrate to form a first groove, which has a base and two inclined sidewalls, ascending to respective bottoms of the gate structures, and are interconnected with the base, respectively; and performing a second etching process on the silicon substrate at the base of the first groove, so as to form a second groove in an inverted -symbol shape, wherein the two inclined sidewalls of the first groove are interconnected with the second groove respectively, and the first etching process is substantially different from the second etching process.
    Type: Grant
    Filed: November 19, 2014
    Date of Patent: June 21, 2016
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Jhen-Cyuan Li, Shui-Yen Lu, Man-Ling Lu, Yu-Cheng Tung, Chung-Fu Chang
  • Publication number: 20160172496
    Abstract: A field effect transistor with epitaxial structures includes a fin-shaped structure and a metal gate across the fin-shaped structure. The metal gate includes a pair of recess regions disposed on two sides of the bottom of the metal gate.
    Type: Application
    Filed: January 19, 2015
    Publication date: June 16, 2016
    Inventors: Chung-Fu Chang, Chun-Hsien Lin, Chen-Yi Weng
  • Publication number: 20160163837
    Abstract: A field effect transistor (FinFET) device includes a substrate, a fin structure, a shallow trench isolation and a gate structure. The fin structure is formed on a surface of the substrate and includes a base fin structure and an epitaxial fin structure formed on the base fin structure. The shallow trench isolation structure is formed on the surface of the substrate and includes a peripheral zone and a concave zone. The peripheral zone physically contacts with the fin structure. The gate structure is disposed on the epitaxial fin structure perpendicularly. A method of fabricating the aforementioned field effect transistor is also provided.
    Type: Application
    Filed: February 18, 2016
    Publication date: June 9, 2016
    Applicant: UNITED MICROELECTRONICS CORPORATION
    Inventors: YEN-LIANG WU, CHUNG-FU CHANG, YU-HSIANG HUNG, SSU-I FU, WEN-JIUN SHEN, MAN-LING LU, CHIA-JONG LIU, YI-WEI CHEN
  • Publication number: 20160163797
    Abstract: The present invention provides a semiconductor structure, comprising a substrate, a gate structure, a source/drain region and at least a dislocation. The gate structure is disposed on the substrate. The source/drain region is disposed in the substrate at two sides of the gate structure. The dislocation is located in the source/drain region, and is asymmetrical relating to a middle axis of the source/drain region.
    Type: Application
    Filed: January 11, 2015
    Publication date: June 9, 2016
    Inventors: Wen-Jiun Shen, Chia-Jong Liu, Chung-Fu Chang, Yen-Liang Wu, Man-Ling Lu, Yi-Wei Chen, Jhen-Cyuan Li
  • Publication number: 20160148998
    Abstract: A FINFET structure is provided. The FINFET structure includes a substrate, a PMOS element, a NMOS element, a STI structure, and a bump structure. The substrate includes a first area and a second area adjacent to the first area. The PMOS element is disposed in the first area of the substrate, and includes at least one first fin structure. The NMOS element is disposed in the second area of the substrate and includes at least one second fin structure. The STI structure is disposed between the first fin structure and the second fin structure. The bump structure is disposed on the STI structure and has a carbon-containing dielectric material.
    Type: Application
    Filed: November 20, 2014
    Publication date: May 26, 2016
    Applicant: UNITED MICROELECTRONICS CORPORATION
    Inventors: YEN-LIANG WU, CHUNG-FU CHANG, WEN-JIUN SHEN, MAN-LING LU, CHIA-JONG LIU, YI-WEI CHEN
  • Patent number: D795364
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: August 22, 2017
    Inventor: Chung-Fu Chang