Patents by Inventor Chung-Fu Chang

Chung-Fu Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9318609
    Abstract: A semiconductor device includes a fin structure, an isolation structure, a gate structure and an epitaxial structure. The fin structure protrudes from the surface of the substrate and includes a top surface and two sidewalls. The isolation structure surrounds the fin structure. The gate structure overlays the top surface and the two sidewalls of a portion of the fin structure, and covers a portion of the isolation structure. The isolation structure under the gate structure has a first top surface, and the isolation structure at two sides of the gate structure has a second top surface. The first top surface is higher than the second top surface. The epitaxial layer is disposed at one side of the gate structure and is in direct contact with the fin structure.
    Type: Grant
    Filed: February 12, 2015
    Date of Patent: April 19, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Hsiang Hung, Ssu-I Fu, Chung-Fu Chang, Cheng-Guo Chen, Chien-Ting Lin
  • Publication number: 20160093737
    Abstract: An etching method adapted to forming grooves in Si-substrate and FinFET transistor manufactured thereof are provided. The etching method includes providing a silicon substrate, at least two gate structures formed on the silicon substrate and at least two gate spacer structures disposed on the silicon substrate; performing a first etching process on the silicon substrate to form a first groove, which has a base and two inclined sidewalls, ascending to respective bottoms of the gate structures, and are interconnected with the base, respectively; and performing a second etching process on the silicon substrate at the base of the first groove, so as to form a second groove in an inverted -symbol shape, wherein the two inclined sidewalls of the first groove are interconnected with the second groove respectively, and the first etching process is substantially different from the second etching process.
    Type: Application
    Filed: November 19, 2014
    Publication date: March 31, 2016
    Applicant: UNITED MICROELECTRONICS CORPORATION
    Inventors: JHEN-CYUAN LI, SHUI-YEN LU, MAN-LING LU, YU-CHENG TUNG, CHUNG-FU CHANG
  • Publication number: 20160071844
    Abstract: A fin-shaped structure includes a substrate having a first fin-shaped structure located in a first area and a second fin-shaped structure located in a second area, wherein the second fin-shaped structure includes a ladder-shaped cross-sectional profile part. The present invention also provides two methods of forming this fin-shaped structure. In one case, a substrate having a first fin-shaped structure and a second fin-shaped structure is provided. A treatment process is performed to modify an external surface of the top of the second fin-shaped structure, thereby forming a modified part. A removing process is performed to remove the modified part through a high removing selectivity to the first fin-shaped structure and the second fin-shaped structure, and the modified part, thereby the second fin-shaped structure having a ladder-shaped cross-sectional profile part is formed.
    Type: Application
    Filed: October 13, 2014
    Publication date: March 10, 2016
    Inventors: Wen-Jiun Shen, Ssu-I Fu, Yen-Liang Wu, Chia-Jong Liu, Yu-Hsiang Hung, Chung-Fu Chang, Man-Ling Lu, Yi-Wei Chen
  • Publication number: 20160064521
    Abstract: A method of manufacturing a semiconductor device including the steps of providing a substrate having first type semiconductor regions and second type semiconductor regions, forming a conformal first epitaxy mask layer on the substrate, forming first type epitaxial layer in the substrate of the first type semiconductor regions, forming a conformal second epitaxy mask layer on the substrate, forming second type epitaxial layer in the substrate of the second type semiconductor regions, and removing the second epitaxy mask layer.
    Type: Application
    Filed: November 8, 2015
    Publication date: March 3, 2016
    Inventors: Yu-Hsiang Hung, Chung-Fu Chang, Chia-Jong Liu, Yen-Liang Wu, Pei-Yu Chou, Home-Been Cheng
  • Publication number: 20160049496
    Abstract: A MOS transistor including a gate structure, an epitaxial spacer and an epitaxial structure is provided. The gate structure is disposed on a substrate. The epitaxial spacer is disposed on the substrate besides the gate structure, wherein the epitaxial spacer includes silicon and nitrogen, and the ratio of nitrogen to silicon is larger than 1.3. The epitaxial structure is disposed in the substrate besides the epitaxial spacer. A semiconductor process includes the following steps for forming an epitaxial structure. A gate structure is formed on a substrate. An epitaxial spacer is formed on the substrate besides the gate structure for defining the position of an epitaxial structure, wherein the epitaxial spacer includes silicon and nitrogen, and the ratio of nitrogen to silicon is larger than 1.3. The epitaxial structure is formed in the substrate besides the epitaxial spacer.
    Type: Application
    Filed: September 25, 2014
    Publication date: February 18, 2016
    Inventors: Man-Ling Lu, Yu-Hsiang Hung, Chung-Fu Chang, Yen-Liang Wu, Wen-Jiun Shen, Chia-Jong Liu, Ssu-I Fu, Yi-Wei Chen
  • Publication number: 20160049467
    Abstract: A field effect transistor (FinFET) device includes a substrate, a fin structure, a shallow trench isolation and a gate structure. The fin structure is formed on a surface of the substrate and includes a base fin structure and an epitaxial fin structure formed on the base fin structure. The shallow trench isolation structure is formed on the surface of the substrate and includes a peripheral zone and a concave zone. The peripheral zone physically contacts with the fin structure. The gate structure is disposed on the epitaxial fin structure perpendicularly. A method of fabricating the aforementioned field effect transistor is also provided.
    Type: Application
    Filed: September 18, 2014
    Publication date: February 18, 2016
    Applicant: UNITED MICROELECTRONICS CORPORATION
    Inventors: YEN-LIANG WU, CHUNG-FU CHANG, YU-HSIANG HUNG, SSU-I FU, WEN-JIUN SHEN, MAN-LING LU, CHIA-JONG LIU, YI-WEI CHEN
  • Publication number: 20160020110
    Abstract: A method of forming a semiconductor device is provided. At least one stacked structure is provided on a substrate. A first spacer material layer, a second spacer material layer, and a third spacer material layer are sequentially formed on the substrate and cover the stacked structure. The first, second, and third spacer material layers are etched to form a tri-layer spacer structure on the sidewall of the stacked structure. The tri-layer spacer structure includes, from one side of the stacked structure, a first spacer, a second spacer, and a third spacer, and a dielectric constant of the second spacer is less than each of a dielectric constant of the first spacer and a dielectric constant of the third spacer.
    Type: Application
    Filed: August 18, 2014
    Publication date: January 21, 2016
    Inventors: Man-Ling Lu, Yu-Hsiang Hung, Chung-Fu Chang, Yen-Liang Wu, Wen-Jiun Shen, Chia-Jong Liu, Ssu-I Fu, Yi-Wei Chen
  • Publication number: 20160020323
    Abstract: A semiconductor device includes a fin structure, an insulating structure, a protruding structure, an epitaxial structure, and a gate structure. The fin structure and the insulating structure are disposed on the substrate. The protruding structure is in direct contact with the substrate and partially protrudes from the insulating structure, and the protruding structure is the fin structure. The epitaxial structure is disposed on a top surface of the fin structure and completely covers the top surface of the fin structure. In addition, the epitaxial structure has a curved top surface. The gate structure covers the fin structure and the epitaxial structure.
    Type: Application
    Filed: August 20, 2014
    Publication date: January 21, 2016
    Inventors: Yen-Liang Wu, Chung-Fu Chang, Yu-Hsiang Hung, Wen-Jiun Shen, Ssu-I Fu, Man-Ling Lu, Chia-Jong Liu, Yi-Wei Chen
  • Publication number: 20160005838
    Abstract: A process for fabricating a fin-type field effect transistor (FinFET) structure is described. A semiconductor substrate is patterned to form a fin. A spacer is formed on the sidewall of the fin. A portion of the fin is removed, such that the spacer and the surface of the remaining fin together define a cavity. A piece of a semiconductor compound is formed from the cavity, wherein the upper portion of the piece of the semiconductor compound laterally extends over the spacer.
    Type: Application
    Filed: September 16, 2015
    Publication date: January 7, 2016
    Inventors: Yu-Hsiang Hung, Ssu-I Fu, Chung-Fu Chang, Yen-Liang Wu, Cho-Han Fan, Chien-Ting Lin
  • Publication number: 20150380506
    Abstract: A replacement gate process is disclosed. A substrate and a dummy gate structure formed on the substrate is provided, wherein the dummy gate structure comprises a dummy layer on the substrate, a hard mask layer on the dummy layer, spacers at two sides of the dummy layer and the hard mask layer, and a contact etch stop layer (CESL) covering the substrate, the spacers and the hard mask layer. The spacers and the CESL are made of the same material. Then, a top portion of the CESL is removed to expose the hard mask layer. Next, the hard mask layer is removed. Afterward, the dummy layer is removed to form a trench.
    Type: Application
    Filed: September 3, 2015
    Publication date: December 31, 2015
    Inventors: Jun-Jie Wang, Po-Chao Tsao, Chia-Jui Liang, Shih-Fang Tzou, Chien-Ting Lin, Cheng-Guo Chen, Ssu-I Fu, Yu-Hsiang Hung, Chung-Fu Chang
  • Patent number: 9224864
    Abstract: A semiconductor device includes a fin structure, an insulating structure, a protruding structure, an epitaxial structure, and a gate structure. The fin structure and the insulating structure are disposed on the substrate. The protruding structure is in direct contact with the substrate and partially protrudes from the insulating structure, and the protruding structure is the fin structure. The epitaxial structure is disposed on a top surface of the fin structure and completely covers the top surface of the fin structure. In addition, the epitaxial structure has a curved top surface. The gate structure covers the fin structure and the epitaxial structure.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: December 29, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yen-Liang Wu, Chung-Fu Chang, Yu-Hsiang Hung, Wen-Jiun Shen, Ssu-I Fu, Man-Ling Lu, Chia-Jong Liu, Yi-Wei Chen
  • Publication number: 20150364568
    Abstract: A fabrication method of a semiconductor structure includes the following steps. First of all, a gate structure is provided on a substrate, and a first material layer is formed on the substrate and the gate structure. Next, boron dopant is implanted to the substrate, at two sides of the gate structure, to form a first doped region, and P type conductive dopant is implanted to the substrate, at the two sides of the gate structure, to form a second doped region. As following, a second material layer is formed on the first material layer. Finally, the second material layer, the first material layer and the substrate at the two sides of the gate structure are etched sequentially, and a recess is formed in the substrate, at the two sides of the gate structure, wherein the recess is positioned within the first doped region.
    Type: Application
    Filed: July 27, 2014
    Publication date: December 17, 2015
    Inventors: Yen-Liang Wu, Chung-Fu Chang, Yu-Hsiang Hung, Ssu-I Fu, Man-Ling Lu, Chia-Jong Liu, Wen-Jiun Shen, Yi-Wei Chen
  • Patent number: 9214395
    Abstract: A method of manufacturing a semiconductor device including the steps of providing a substrate having first type semiconductor regions and second type semiconductor regions, forming a conformal first epitaxy mask layer on the substrate, forming first type epitaxial layer in the substrate of the first type semiconductor regions, forming a conformal second epitaxy mask layer on the substrate, forming second type epitaxial layer in the substrate of the second type semiconductor regions, and removing the second epitaxy mask layer.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: December 15, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Hsiang Hung, Chung-Fu Chang, Chia-Jong Liu, Yen-Liang Wu, Pei-Yu Chou, Home-Been Cheng
  • Publication number: 20150357436
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a gate structure on the substrate; performing a first dry etching process to form a recess in the substrate adjacent to the gate structure; and performing a second dry etching process to expand the recess.
    Type: Application
    Filed: July 7, 2014
    Publication date: December 10, 2015
    Inventors: Wen-Jiun Shen, Chia-Jong Liu, Yi-Wei Chen, Ssu-I Fu, Chung-Fu Chang, Yu-Hsiang Hung, Yen-Liang Wu, Man-Ling Lu
  • Patent number: 9166024
    Abstract: A process for fabricating a fin-type field effect transistor (FinFET) structure is described. A semiconductor substrate is patterned to form a fin. A spacer is formed on the sidewall of the fin. A portion of the fin is removed, such that the spacer and the surface of the remaining fm together define a cavity. A piece of a semiconductor compound is formed from the cavity, wherein the upper portion of the piece of the semiconductor compound laterally extends over the spacer.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: October 20, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Yu-Hsiang Hung, Ssu-I Fu, Chung-Fu Chang, Yen-Liang Wu, Cho-Han Fan, Chien-Ting Lin
  • Patent number: 9159798
    Abstract: A replacement gate process is disclosed. A substrate and a dummy gate structure formed on the substrate is provided, wherein the dummy gate structure comprises a dummy layer on the substrate, a hard mask layer on the dummy layer, spacers at two sides of the dummy layer and the hard mask layer, and a contact etch stop layer (CESL) covering the substrate, the spacers and the hard mask layer. The spacers and the CESL are made of the same material. Then, a top portion of the CESL is removed to expose the hard mask layer. Next, the hard mask layer is removed. Afterward, the dummy layer is removed to form a trench.
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: October 13, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Jun-Jie Wang, Po-Chao Tsao, Chia-Jui Liang, Shih-Fang Tzou, Chien-Ting Lin, Cheng-Guo Chen, Ssu-I Fu, Yu-Hsiang Hung, Chung-Fu Chang
  • Publication number: 20150283420
    Abstract: A belt pulling exercise apparatus includes an adjusting belt, having a first ladder lock disposed thereon, and one end of the adjusting belt is passed through a first ring; two connecting belts, two first ends of the two connecting belts are fastened to the first ring simultaneously, two second ends of each connecting belts opposite to the first ends are respectively fastened to a third ring, and two second rings are respectively fastened to an upper surface of each connecting belt between the first end and the second end; two elastic rope assemblies, each elastic rope assembly is arranged corresponding to each connecting belt, and two ends of each elastic rope assembly are respectively connected to the second ring and the third ring of each corresponding connecting belt; and two hand grips, each hand grip is arranged at each corresponding connecting belt and each corresponding elastic rope assembly.
    Type: Application
    Filed: December 17, 2014
    Publication date: October 8, 2015
    Inventor: CHUNG-FU CHANG
  • Publication number: 20150255563
    Abstract: A method for manufacturing a semiconductor device is provided, comprising steps of providing a substrate with an underlying layer formed thereon; forming a gate layer overlying the underlying layer; and forming a multi-layer hard mask layer on the gate layer, and the multi-layer hard mask layer comprising a plurality of material layers and a top hard mask formed on the material layers, wherein the gate layer and the top hard mask contain the same element, such as silicon.
    Type: Application
    Filed: March 4, 2014
    Publication date: September 10, 2015
    Applicant: United Microelectronics Corp.
    Inventors: Yen-Liang Wu, Chung-Fu Chang, Yu-Hsiang Hung, Man-Ling Lu, Cho-Han Fan, Ssu-I Fu, Chen-Ming Huang
  • Patent number: 9070710
    Abstract: A semiconductor process includes the following steps. A substrate is provided. At least a fin-shaped structure is formed on the substrate and a gate structure partially overlapping the fin-shaped structure is formed. Subsequently, a dielectric layer is blanketly formed on the substrate, and a part of the dielectric layer is removed to form a first spacer on the fin-shaped structure and a second spacer besides the fin-shaped structure. Furthermore, the second spacer and a part of the fin-shaped structure are removed to form at least a recess at a side of the gate structure, and an epitaxial layer is formed in the recess.
    Type: Grant
    Filed: June 7, 2013
    Date of Patent: June 30, 2015
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ssu-I Fu, Cheng-Guo Chen, Yu-Hsiang Hung, Chung-Fu Chang, Chien-Ting Lin
  • Publication number: 20150155386
    Abstract: A semiconductor device includes a fin structure, an isolation structure, a gate structure and an epitaxial structure. The fin structure protrudes from the surface of the substrate and includes a top surface and two sidewalls. The isolation structure surrounds the fin structure. The gate structure overlays the top surface and the two sidewalls of a portion of the fin structure, and covers a portion of the isolation structure. The isolation structure under the gate structure has a first top surface, and the isolation structure at two sides of the gate structure has a second top surface. The first top surface is higher than the second top surface. The epitaxial layer is disposed at one side of the gate structure and is in direct contact with the fin structure.
    Type: Application
    Filed: February 12, 2015
    Publication date: June 4, 2015
    Inventors: Yu-Hsiang Hung, Ssu-I Fu, Chung-Fu Chang, Cheng-Guo Chen, Chien-Ting Lin