Patents by Inventor Chung-Lung K. Shum

Chung-Lung K. Shum has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Non-default instruction handling within transaction
    Patent number: 10310855
    Abstract: Embodiments relate to non-default instruction handling within a transaction. An aspect includes entering a transaction, the transaction comprising a first plurality of instructions and a second plurality of instructions, wherein a default manner of handling of instructions in the transaction is one of atomic and non-atomic. Another aspect includes encountering a non-default specification instruction in the transaction, wherein the non-default specification instruction comprises a single instruction that specifies the second plurality of instructions of the transaction for handling in a non-default manner comprising one of atomic and non-atomic, wherein the non-default manner is different from the default manner. Another aspect includes handling the first plurality of instructions in the default manner. Yet another aspect includes handling the second plurality of instructions in the non-default manner.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: June 4, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jonathan D. Bradbury, Michael K. Gschwind, Maged M. Michael, Eric M. Schwarz, Valentina Salapura, Chung-Lung K. Shum
  • EMPLOYING A STACK ACCELERATOR FOR STACK-TYPE ACCESSES
    Publication number: 20190163492
    Abstract: A stack accelerator is employed for stack-type accesses. An instruction stream is scanned for stack-type accesses. These stack-type accesses may include push and pop stack operations. Based on identifying a stack-type access in the instruction stream, memory operations are replaced with one or more operations that access a stack in a stack accelerator.
    Type: Application
    Filed: November 28, 2017
    Publication date: May 30, 2019
    Inventors: Michael K. Gschwind, Chung-Lung K. Shum, Timothy J. Slegel, Jonathan D. Bradbury
  • Hybrid tracking of transaction read and write sets
    Patent number: 10293534
    Abstract: Tracking a processor instruction is provided to limit a speculative mis-prediction. A non-speculative read set indication and/or write set indication are maintained for a transaction. In addition, a queue(s) of at least one address corresponding to a speculatively executed instruction is maintained. For a received request from a remote processor, a transaction resolution process takes place, and a resolution is performed if an address match in the queue is detected. The resolution includes to hold a response to the receive request until the speculative instruction is committed or flushed.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: May 21, 2019
    Assignee: International Business Machines Corporation
    Inventors: Michael K. Gschwind, Valentina Salapura, Chung-Lung K. Shum
  • CONCURRENT MODIFICATION OF SHARED CACHE LINE BY MULTIPLE PROCESSORS
    Publication number: 20190146916
    Abstract: A shared cache line is concurrently modified by multiple processors of a computing environment. The concurrent modification is performed based, at least, on receiving one or more architected instructions (Fetch due to Non-Coherent Store instructions) that permit multiple processors to concurrently update the shared cache line absent obtaining a lock or having exclusive ownership of the data.
    Type: Application
    Filed: November 10, 2017
    Publication date: May 16, 2019
    Inventors: Nicholas C. Matsakis, Craig R. Walters, Jane H. Bartik, Chung-Lung K. Shum, Elpida Tzortzatos
  • HINT INSTRUCTION FOR MANAGING TRANSACTIONAL ABORTS IN TRANSACTIONAL MEMORY COMPUTING ENVIRONMENTS
    Publication number: 20190138346
    Abstract: When executed, a transaction-hint instruction specifies a transaction-count-to-completion (CTC) value for a transaction. The CTC value indicates how far a transaction is from completion. The CTC may be a number of instructions to completion or an amount of time to completion. The CTC value is adjusted as the transaction progresses. When a disruptive event associated with inducing transactional aborts, such as an interrupt or a conflicting memory access, is identified while processing the transaction, processing of the disruptive event is deferred if the adjusted CTC value satisfies deferral criteria. If the adjusted CTC value does not satisfy deferral criteria, the transaction is aborted and the disruptive event is processed.
    Type: Application
    Filed: January 2, 2019
    Publication date: May 9, 2019
    Inventors: Fadi Y. Busaba, Harold W. Cain, III, Dan F. Greiner, Michael Karl Gschwind, Maged M. Michael, Valentina Salapura, Chung-Lung K. Shum, Timothy J. Slegel
  • Fingerprint-initiated trace extraction
    Patent number: 10282276
    Abstract: Techniques relate to fingerprint-initiated trace extraction. A determination is made of whether a fingerprint is present in software that is currently executing on a processor of a computer system. The fingerprint comprises a representation of a sequence of behavior that occurs in the processor while the software is executing. In response to determining that the fingerprint is not present in the software currently executing on the processor, monitoring continues for the software executing on the processor to determine whether the fingerprint is present. In response to determining that the fingerprint is present in the software executing on the processor, a trace is triggered of a code segment of the software corresponding to when the fingerprint is recognized. The trace is for a record of instructions of the code segment of the software.
    Type: Grant
    Filed: January 16, 2017
    Date of Patent: May 7, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jonathan D. Bradbury, Giles R. Frazier, Michael Karl Gschwind, Christian Jacobi, Anthony Saporito, Chung-Lung K. Shum
  • Mechanism for creating friendly transactions with credentials
    Patent number: 10270775
    Abstract: One or more transactions may request or be assigned tokens within a transactional memory environment. A transaction may be created by at least one thread. A first transaction that includes a first token type may be received. A request may be received for a for a potential conflict check between the first transaction and a second transaction. In response to receiving the transaction potential conflict check, the first transaction and the second transaction are determined to be conflicting or not conflicting. The second transaction is assigned a token type in response to the determination of the transaction potential conflict check between the first transaction and the second transaction.
    Type: Grant
    Filed: May 3, 2016
    Date of Patent: April 23, 2019
    Assignee: International Business Machines Corporation
    Inventors: Jonathan D. Bradbury, Fadi Y. Busaba, Michael Karl Gschwind, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum
  • Mechanism for creating friendly transactions with credentials
    Patent number: 10270773
    Abstract: One or more transactions may request or be assigned tokens within a transactional memory environment. A transaction may be created by at least one thread. A first transaction that includes a first token type may be received. A request may be received for a for a potential conflict check between the first transaction and a second transaction. In response to receiving the transaction potential conflict check, the first transaction and the second transaction are determined to be conflicting or not conflicting. The second transaction is assigned a token type in response to the determination of the transaction potential conflict check between the first transaction and the second transaction.
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: April 23, 2019
    Assignee: International Business Machines Corporation
    Inventors: Jonathan D. Bradbury, Fadi Y. Busaba, Michael Karl Gschwind, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum
  • Bypassing memory access for a load instruction using instruction address mapping
    Patent number: 10261791
    Abstract: Systems, methods, and computer-readable media are disclosed for executing a predicted load that bypasses memory access for a load instruction. A first physical register that is predicted as storing a value to be loaded by the load instruction is identified and the value stored in the first physical register is copied to a second physical register for use by a consumer operation. A predicted store instruction corresponding to the load instruction is identified and a mapping table is accessed to obtain data associated with the predicted store instruction. The data is evaluated to determine whether the predicted load meets dependency constraints. As a result of execution of the predicted load, the consumer operation can utilize the data stored in the first physical register directly and bypass the cache memory access that would otherwise be required to execute the load instruction.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: April 16, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brian R. Prasky, David A. Schroter, Chung-Lung K. Shum, Corey C. Stappenbeck
  • NON-COHERENT READ IN A STRONGLY CONSISTENT CACHE SYSTEM FOR FREQUENTLY READ BUT RARELY UPDATED DATA
    Publication number: 20190108125
    Abstract: A technique relates to enabling a multiprocessor computer system to make a non-coherent request for a cache line. A first processor core sends a non-coherent fetch to a cache. In response to a second processor core having exclusive ownership of the cache line in the cache, the first processor core receives a stale copy of the cache line in the cache based on the non-coherent fetch. The non-coherent fetch is configured to obtain the stale copy for a predefined use. Cache coherency is maintained for the cache, such that the second processor core continues to have exclusive ownership of the cache line while the first processor core receives the stale copy of the cache line.
    Type: Application
    Filed: October 6, 2017
    Publication date: April 11, 2019
    Inventors: Jane H. BARTIK, Nicholas C. MATSAKIS, Chung-Lung K. SHUM, Craig R. WALTERS
  • NON-COHERENT READ IN A STRONGLY CONSISTENT CACHE SYSTEM FOR FREQUENTLY READ BUT RARELY UPDATED DATA
    Publication number: 20190108126
    Abstract: A technique relates to enabling a multiprocessor computer system to make a non-coherent request for a cache line. A first processor core sends a non-coherent fetch to a cache. In response to a second processor core having exclusive ownership of the cache line in the cache, the first processor core receives a stale copy of the cache line in the cache based on the non-coherent fetch. The non-coherent fetch is configured to obtain the stale copy for a predefined use. Cache coherency is maintained for the cache, such that the second processor core continues to have exclusive ownership of the cache line while the first processor core receives the stale copy of the cache line.
    Type: Application
    Filed: November 8, 2017
    Publication date: April 11, 2019
    Inventors: Jane H. BARTIK, Nicholas C. MATSAKIS, Chung-Lung K. SHUM, Craig R. WALTERS
  • Mechanism for creating friendly transactions with credentials
    Patent number: 10255189
    Abstract: A transactional memory execution environment receives a first request from a first transaction to access a cache line. A first request is received from a first transaction to access a cache line. The cache line is determined to be used by a second transaction. The first transaction and the second transaction opt-in to a transaction potential conflict check. The transaction potential conflict check determines if the first transaction and the second transaction are in a conflicting coherent state. The conflicting coherent state occurs when the first transaction is modifying the cache line used by the second transaction. The first transaction is allowed access to the cache line without aborting the second transaction in response to a determination that the first transaction and the second transaction are compatible from the transaction potential conflict check.
    Type: Grant
    Filed: May 3, 2016
    Date of Patent: April 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Jonathan D. Bradbury, Fadi Y. Busaba, Michael Karl Gschwind, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum
  • PREFETCH INSENSITIVE TRANSACTIONAL MEMORY
    Publication number: 20190087317
    Abstract: Processing prefetch memory operations and transactions. A local processor receives a prefetch request from a remote processor. Prior to execution of the prefetch request, determining whether a priority of the remote processor is greater than a priority of a local processor. The write prefetch request is executed in response to a to a determination that the priority of the remote processor is greater than the priority of the local processor. Prefetch data produced by execution of the prefetch request is provided to the remote processor.
    Type: Application
    Filed: November 12, 2018
    Publication date: March 21, 2019
    Inventors: Michael Karl Gschwind, Valentina Salapura, Chung-Lung K. Shum, Timothy J. Slegel
  • Dynamic releasing of cache lines
    Patent number: 10235201
    Abstract: A computer-implemented method includes, in a transactional memory environment, identifying a transaction and identifying one or more cache lines. The cache lines are allocated to the transaction. A cache line record is stored. The cache line record includes a reference to the one or more cache lines. An indication is received. The indication denotes a request to demote the one or more cache lines. The cache line record is retrieved, and the one or more cache lines are released. A corresponding computer program product and computer system are also disclosed.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: March 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Jonathan D. Bradbury, Michael Karl Gschwind, Chung-Lung K. Shum, Timothy J. Slegel
  • Load register on condition immediate or immediate instruction
    Patent number: 10235168
    Abstract: A data processor comprising a plurality of registers, and instruction execution circuitry having an associated instruction set, wherein the instruction set includes an instruction specifying at least a mask operand, a register operand and an immediate value operand, and the instruction execution circuitry, in response to an instance of the instruction, determines a Boolean value based on the mask operand and sets a respective one of a plurality of registers specified by the register operand of the instance to a value of the immediate value operand if the Boolean value is true. The instruction execution circuitry, in response to the instance of the instruction, may set the respective one of the plurality of registers specified by the register operand of the instance to zero if the Boolean value is false.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: March 19, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Wolfgang Gellerich, Martin Schwidefsky, Chung-Lung K. Shum, Kai Weber
  • Mechanism for creating friendly transactions with credentials
    Patent number: 10235297
    Abstract: A transactional memory execution environment receives a first request from a first transaction to access a cache line. A first request is received from a first transaction to access a cache line. The cache line is determined to be used by a second transaction. The first transaction and the second transaction opt-in to a transaction potential conflict check. The transaction potential conflict check determines if the first transaction and the second transaction are in a conflicting coherent state. The conflicting coherent state occurs when the first transaction is modifying the cache line used by the second transaction. The first transaction is allowed access to the cache line without aborting the second transaction in response to a determination that the first transaction and the second transaction are compatible from the transaction potential conflict check.
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: March 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Jonathan D. Bradbury, Fadi Y. Busaba, Michael Karl Gschwind, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum
  • CONTROLLING A RATE OF PREFETCHING BASED ON BUS BANDWIDTH
    Publication number: 20190079872
    Abstract: Controlling a rate of prefetching based on bus bandwidth. A determination is made as to whether a rate of prefetching data from memory into a cache is to be changed. This determination is based on bus utilization. Based on determining that the rate is to be changed, the rate of prefetching is changed.
    Type: Application
    Filed: November 14, 2017
    Publication date: March 14, 2019
    Inventors: Jonathan D. Bradbury, Michael K. Gschwind, Christian Jacobi, Chung-Lung K. Shum
  • CONTROLLING A RATE OF PREFETCHING BASED ON BUS BANDWIDTH
    Publication number: 20190079871
    Abstract: Controlling a rate of prefetching based on bus bandwidth. A determination is made as to whether a rate of prefetching data from memory into a cache is to be changed. This determination is based on bus utilization. Based on determining that the rate is to be changed, the rate of prefetching is changed.
    Type: Application
    Filed: September 12, 2017
    Publication date: March 14, 2019
    Inventors: Jonathan D. Bradbury, Michael K. Gschwind, Christian Jacobi, Chung-Lung K. Shum
  • PREFETCH INSENSITIVE TRANSACTIONAL MEMORY
    Publication number: 20190079858
    Abstract: Processing prefetch memory operations and transactions. A local processor receives a write prefetch request from a remote processor. Prior to execution of a write prefetch request received from a remote processor, determining whether a priority of the write prefetch request is greater than a priority of a pending transaction of a local processor. The write prefetch request is executed in response to a determination that the priority of the write prefetch request is greater than the priority of a pending transaction. Prefetch data produced by execution of the write prefetch request is provided to the remote processor.
    Type: Application
    Filed: November 12, 2018
    Publication date: March 14, 2019
    Inventors: Michael Karl Gschwind, Valentina Salapura, Chung-Lung K. Shum, Timothy J. Slegel
  • DEFERRED RESPONSE TO A PREFETCH REQUEST
    Publication number: 20190073309
    Abstract: Modifying prefetch request processing. A prefetch request is received by a local computer from a remote computer. The local computer responds to a determination that execution of the prefetch request is predicted to cause an address conflict during an execution of a transaction of the local processor by comparing a priority of the prefetch request with a priority of the transaction. Based on a result of the comparison, the local computer modifies program instructions that govern execution of the program instructions included in the prefetch request to include program instruction to perform one or both of: (i) a quiesce of the prefetch request prior to execution of the prefetch request, and (ii) a delay in execution of the prefetch request for a predetermined delay period.
    Type: Application
    Filed: October 30, 2018
    Publication date: March 7, 2019
    Inventors: Michael Karl Gschwind, Valentina Salapura, Chung-Lung K. Shum