Abstract: A garbage collection facility is provided for memory management within a computer. The facility implements, in part, grouping of infrequently accessed data units in a designated transient memory area, and includes designating an area of the memory as a transient memory area and an area as a conventional memory area, and counting, for each data unit in the transient or conventional memory areas a number of accesses to the data unit. The counting provides a respective access count for each data unit. For each data unit in the transient memory area or the conventional memory area, a determination is made whether the respective access count is below a transient threshold ascertained to separate frequently accessed data units and infrequently used data units. Data units with respective access counts below the transient threshold are grouped together as transient data units within the transient memory area.

Abstract: Preventing a prefetch memory operation from causing a transaction to abort by receiving by a local processor a prefetch request from a remote processor. Determining whether the prefetch request conflicts with a transaction of the local processor. Responding to at least one of i) a determination that the local processor has no transaction, and ii) a determination that the prefetch request does not conflict with a transaction of the local processor, by providing a requested prefetch data. Responding to a determination that the prefetch request conflicts with a transaction of the local processor by determining an evaluation of the prefetch request. Performing at least one of i) an abort of the prefetch request, ii) a quiesce the prefetch request, iii) a delay in the processing of the prefetch request for a delay period, and iv) an execution of the prefetch request based on the evaluation the prefetch request.

Abstract: Tracking a processor instruction is provided to limit a speculative mis-prediction. A non-speculative read set indication and/or write set indication are maintained for a transaction. The indication(s) are stored in cache. In addition, a queue(s) of at least one address corresponding to a speculatively executed instruction is maintained. For a received request from a processor, a transaction resolution process takes place, and a resolution is performed if an address match in the queue is detected. The resolution includes to hold a response to the receive request until the speculative instruction is committed or flushed.

Abstract: A processor in a multi-processor configuration is configured perform dynamic address translation from logical addresses to real address and to detect memory conflicts for shared logical memory in transactional memory based on logical (virtual) addresses comparisons.

Abstract: Selective register allocation. Based on determining that an unused physical register is unavailable for allocation, a physical register to be used for allocation is chosen from a selective group of physical registers. The selective group of physical registers is associated with a snapshot of one type of snapshot selected from a plurality of types of snapshots. The snapshot maps physical registers to architected registers. The physical register chosen for allocation is allocated.

Abstract: Register restoration invalidation based on a context switch. A context switch from one executing entity to another executing entity is detected. Based on detecting the context switch, an entry of a snapshot stack to be invalidated is selected. The entry of the snapshot stack provides an indication of a snapshot. The snapshot includes an assignment of one or more physical registers to one or more architected registers. The entry of the snapshot stack selected for invalidation is invalidated.

Abstract: A load request to restore a plurality of architected registers is obtained. Based on obtaining the load request, one or more architected registers of the plurality of architected registers are restored. The restoring uses a snapshot that maps architected registers to physical registers to replace one or more physical registers currently assigned to the one or more architected registers with one or more physical registers of the snapshot corresponding to the one or more architected registers.

Abstract: Register restoration or register reloading is selected. A restoration request to restore a plurality of architected registers is obtained. A determination is made as to whether a snapshot associated with the plurality of architected registers is valid. The snapshot provides in-core values for the plurality of architected registers. Based on the snapshot being valid, a determination is made as to whether the snapshot is to be used to recover an individual architected register of the plurality of architected registers. Based on determining the snapshot is to be used, the snapshot is used to recover the individual architected register. Based on determining the snapshot is not to be used, memory is used to recover the individual architected register.

Abstract: Register restoration using recovery buffers. A restore request initiated by an application to restore one or more registers indicated by the restore request is obtained. The one or more registers are restored using a recovery buffer. The restoring scans the recovery buffer for the one or more registers indicated by the restore request, and restores the one or more registers using one or more values obtained from the recovery buffer.

Abstract: A reload multiple instruction is used to restore a set of architected registers saved by a spill multiple instruction. The reload multiple instruction is executed, and the executing includes determining the set of architected registers to be restored, which is specified by the reload multiple instruction. The set of architected registers is restored from a selected snapshot that maps architected registers to physical registers. The restoring replaces one or more physical registers currently assigned to one or more architected registers of the set of architected registers with one or more physical registers of the selected snapshot corresponding to the set of architected registers.

Abstract: One or more architected registers are restored from a snapshot previously taken of the one or more architected registers. The snapshot indicates one or more physical registers previously assigned to the one or more architected registers. The restoring replaces the one or more physical registers currently assigned to the one or more architected registers with the one or more physical registers previously assigned to the one or more architected registers as indicated by the snapshot. A determination is made as to the validity of the one or more architected registers restored using the snapshot. The determining validity includes checking memory locations associated with the one or more architected registers to determine whether contents of the one or more architected registers have changed since the snapshot was taken. If the contents of the one or more architected registers have not changed, the one or more architected registers are valid.

Abstract: Sharing snapshots between restoration and recovery. A snapshot to be used for recovery and restoration is obtained. The snapshot includes restoration state for a plurality of architected registers. The plurality of architected registers includes one or more architected registers associated with an instruction to alter an execution path and one or more architected registers associated with a save request. At least one architected register of the plurality of architected registers is restored, based on a request. The request is a recovery request to recover at least one architected register associated with the instruction to alter the execution path or a restoration request to restore at least one architected register associated with the save request.

Abstract: Prevention of a prefetch memory operation from causing a transaction to abort. A local processor receives a prefetch request from a remote processor. Prior to execution of the prefetch request, a processor determines whether the prefetch request conflicts with a transaction of the local processor. A processor responds to a determination that the priority of the remote processor is greater than priority of the local processor by (i) aborting the transaction (ii) executing the prefetch request, and (iii) providing requested prefetch data to the remote processor.

Abstract: Prevention of a prefetch memory operation from causing a transaction to abort. A local processor receives a prefetch request from a remote processor. Prior to execution of the prefetch request, a processor determines whether the prefetch request conflicts with a transaction of the local processor. A processor responds to a determination that the priority of the prefetch request is greater than priority of the transaction, by (i) aborting the transaction (ii) executing the prefetch request, and (iii) providing requested prefetch data to the remote processor.

Abstract: A transactional memory system salvages a hardware lock elision (HLE) transaction. A processor of the transactional memory system, based on a detection of a pending point-of-failure in a code region during HLE transactional execution, stops HLE transactional execution prior to the pending point-of-failure in the code region. The processor, based on information about a lock elided, commits a speculative state of the stopped HLE transactional execution that is stored, at least in part, in a gathering store cache. The processor starts non-transactional execution at the point of failure in the code region.

Abstract: An instruction stream includes a transactional code region. The transactional code region includes a latent modification instruction (LMI), a next sequential instruction (NSI) following the LMI, and a set of target instructions following the NSI in program order. Each target instruction has an associated function, and the LMI at least partially specifies a substitute function for the associated function. A processor executes the LMI, the NSI, and at least one of the target instructions, employing the substitute function at least partially specified by the LMI. The LMI, the NSI, and the target instructions may be executed by the processor in sequential program order or out of order.

Abstract: Systems, methods, and computer-readable media are disclosed for executing a predicted load that bypasses memory access for a load instruction. A first physical register that is predicted as storing a value to be loaded by the load instruction is identified and the value stored in the first physical register is copied to a second physical register for use by a consumer operation. A predicted store instruction corresponding to the load instruction is identified and a mapping table is accessed to obtain data associated with the predicted store instruction. The data is evaluated to determine whether the predicted load meets dependency constraints. As a result of execution of the predicted load, the consumer operation can utilize the data stored in the first physical register directly and bypass the cache memory access that would otherwise be required to execute the load instruction.

Abstract: Prevention of a prefetch memory operation from causing a transaction to abort. A local processor receives a prefetch request from a remote processor. A processor determines whether the prefetch request conflicts with a transaction of the local processor. A processor responds to at least one of i) a determination that the local processor has no transaction, and ii) a determination that the prefetch request does not conflict with a transaction by providing a requested prefetch data by providing a requested prefetch data. A processor responds to a determination that the prefetch request conflicts with a transaction by suppressing a processing of the prefetch request.

Abstract: An instruction stream includes a transactional code region. The transactional code region includes a latent modification instruction (LMI), a next sequential instruction (NSI) following the LMI, and a set of target instructions following the NSI in program order. Each target instruction has an associated function, and the LMI at least partially specifies a substitute function for the associated function. A processor executes the LMI, the NSI, and at least one of the target instructions, employing the substitute function at least partially specified by the LMI. The LMI, the NSI, and the target instructions may be executed by the processor in sequential program order or out of order.

Abstract: Improving the tracking of read sets and write sets associated with cache lines of a transaction in a pipelined processor executing memory instructions having the read sets and write sets associated with the cache lines is provided. Included is active read set and write set cache indicators associated with the memory operation of executing memory instructions and associated with a recovery pool based on memory instructions being not-speculative are updated when the memory instruction is not-newer in program order than an un-resolved branch instruction. Based on encountering a speculative branch instruction in the processor pipeline, a representation of the active read sets and write sets is copied to the recovery pool. Based on completing the speculative branch instruction, updating the active read sets and write sets from the representations copied to the recovery pool associated with the branch instruction upon a detection of a misprediction.