Abstract: Semiconductor device structures and methods for manufacturing the same are provided. The semiconductor device structure includes a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a first electrode, a second electrode, a gate structure and a temperature sensitive component. The first nitride semiconductor layer is disposed on the substrate. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer and has a bandgap greater than that of the first nitride semiconductor layer. The first electrode, the second electrode and the gate structure are disposed on the second nitride semiconductor layer. The temperature sensitive component is disposed external to a region between the gate structure and the first electrode along a first direction in parallel to an interface of the first nitride semiconductor layer and the second nitride semiconductor layer.

Abstract: An integrated semiconductor device includes a substrate, semiconductor circuit layers, a first insulating layer, a second insulating layer, and an interconnection layer. The semiconductor circuit layers are disposed above the substrate. The semiconductor circuit layers have device portions and isolating portions, and the isolating portions are located among the device portions. The first insulating layer is disposed on the semiconductor circuit layers, and the second insulating layer is disposed on the first insulating layer, and the interconnection layer is disposed on the semiconductor circuit layers. The interconnection layer penetrates the first and second insulating layers to electrically connect the device portions of the semiconductor circuit layers. The second insulating layer or the first and second insulating layers collectively form one or more isolating structures above the isolating portion of the semiconductor circuit layers.

Abstract: An integrated semiconductor device includes a substrate, semiconductor circuit layers, an insulating material, and an interconnection layer. The semiconductor circuit layers are disposed above the substrate. The semiconductor circuit layers have device portions and isolating portions, and the isolating portions are located among the device portions. The insulating material is disposed on the semiconductor circuit layers, and the interconnection layer is embedded in the insulating material and electrically connected to the semiconductor circuit layers. The isolating portions provide electrical isolation between adjacent device portions. The interconnection layer has circuits embedded in the insulating material on the device portions. The insulating material has isolating structures raised from top surfaces of the circuits on the device portion, and some of the semiconductor circuit layers form at least one heterojunction.

Abstract: A movable battery replacing platform includes a travel-driving portion used for driving the movable battery replacing platform to move on the ground; a lifting portion mounted on the travel-driving portion, for lifting a battery during the replacement of the battery; and a battery mounting portion mounted on the top of the lifting portion, for placing a battery to be replaced or a replaced battery. The battery mounting porting is provided with a battery replacing device. The device can use an unlocking device to unlock a battery locked on the bottom of an electric vehicle, automatically aligning an unlocking point of a battery locking mechanism and realizing automatic unlocking in the movement. The angle of an upper board relative to the battery unlocking position can be adjusted by a movement actuating device, so that the unlocking point of the battery can automatically fit where the movable battery replacing platform remains still.

Abstract: Disclosed is an unlocking device, battery replacing platform and movable battery replacing platform. The unlocking device comprises: a guide rail; a movable seat mounted on the guide rail; an unlocking ejector rod vertically mounted on the movable seat; and a driving member to drive the movable seat to move horizontally along a plane of the guide rail, the driving member is a driving push rod; the movable seat mounted on the guide rail includes a fixing cylinder fixed vertically mounted direct on the movable seat, and the unlocking ejector rod is movably mounted inside of the fixing cylinder, and a second spring is provided in the fixing cylinder, the second spring is configured to apply an upward thrust to the unlocking ejector rod. The unlocking ejector rod can be controlled to move on the predetermined rail, and the battery locking mechanism on the electric vehicle can be automatically unlocked.

Abstract: A nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a third nitride-based semiconductor layer, a passivation layer, a gate insulator layer, and a gate electrode. The first nitride-based semiconductor layer includes at least two doped barrier regions defining an aperture between the doped barrier regions. The second nitride-based semiconductor layer is disposed over first nitride-based semiconductor layer. The third nitride-based semiconductor layer is disposed on the second nitride-based semiconductor layer and has a bandgap higher than a bandgap of the second nitride-based semiconductor layer. The passivation layer is disposed over the third nitride-based semiconductor layer, in which a vertical projection of the passivation layer on the first nitride-based semiconductor layer is spaced apart from the aperture. The gate insulator layer is disposed over the third nitride-based semiconductor layer.

Abstract: A nitride-based semiconductor device includes a first nitride-based semiconductor layer, a nitride-based multiple semiconductor layer, a gate electrode, a gate insulator layer, and a source electrode. The first nitride-based semiconductor layer includes a drift region and at least two doped barrier regions defining an aperture in the drift region. The nitride-based multiple semiconductor layer structure is disposed over the first nitride-based semiconductor layer and has a first heterojunction and a second heterojunction which are separated from each other. The gate electrode is received by the nitride-based multiple semiconductor layer structure and vertically aligns with the aperture in the drift region. The gate insulator layer is disposed between the nitride-based multiple semiconductor layer structure and the gate electrode.

Abstract: An integrated semiconductor device includes a substrate, semiconductor circuit layers, a first insulating layer, a second insulating layer, and an interconnection layer. The semiconductor circuit layers are disposed above the substrate. The semiconductor circuit layers have device portions and isolating portions, and the isolating portions are located among the device portions. The first insulating layer is disposed on the semiconductor circuit layers, and the second insulating layer is disposed on the first insulating layer, and the interconnection layer is disposed on the semiconductor circuit layers. The interconnection layer penetrates the first and second insulating layers to electrically connect the device portions of the semiconductor circuit layers. The second insulating layer or the first and second insulating layers collectively form one or more isolating structures above the isolating portion of the semiconductor circuit layers.

Abstract: Semiconductor device structures and methods for manufacturing the same are provided. The semiconductor device structure includes a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a barrier layer, a third nitride semiconductor layer and a gate structure. The first nitride semiconductor layer is disposed on the substrate. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer and has a bandgap greater than that of the first nitride semiconductor layer. The barrier layer is disposed on the second nitride semiconductor layer and has a bandgap greater than that of the second nitride semiconductor layer. The third nitride semiconductor layer is doped with impurity and disposed on the barrier layer. The gate structure is disposed on the third nitride semiconductor layer.

Abstract: A flip-chip semiconductor package with improved heat dissipation capability and low package profile is provided. The package comprises a heat sink having a plurality of heat dissipation fins and a plurality of heat dissipation leads. The heat dissipation leads are connected to a plurality of thermally conductive vias of a substrate so as to provide thermal conductivity path from the heatsink to the substrate as well as support the heatsink to relieve compressive stress applied to a semiconductor die by the heatsink. The package further comprises an encapsulation layer configured to cover the heat dissipation leads of the heat sink and expose the heat dissipation fins of the heat sink.

Abstract: The present disclosure provides a nitride-based bidirectional switching device with substrate potential management capability. The device has a control node, a first power/load node, a second power/load node and a main substrate, and comprises: a nitride-based bilateral transistor and a substrate potential management circuit configured for managing a potential of the main substrate. By implementing the substrate potential management circuit, the substrate potential can be stabilized to a lower one of the potentials of the first source/drain and the second source/drain of the bilateral transistor no matter in which directions the bidirectional switching device is operated. Therefore, the bilateral transistor can be operated with a stable substrate potential for conducting current in both directions.

Abstract: The present disclosure provides a semiconductor module comprising a semiconductor device removably pressed-fit in a cavity formed in a printed circuit board and methods for manufacturing the same. The semiconductor device and the cavity of the printed circuit board can cooperate with each other and act as an electrical plug and an electrical socket respectively. Soldering the semiconductor device on the printed circuit board can be avoided. Therefore, the packaging process can be more flexible and reliability issues with solder joints can be eliminated. Moreover, heatsink can be mounted on top and/or bottom of the semiconductor device after being received in the cavity of the printed circuit board. Thermal dissipation efficiency can be greatly enhanced.

Abstract: A semiconductor device includes a substrate, a channel layer, a barrier layer, a gate, a strained layer and a passivation layer. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The gate is disposed on the barrier layer. The strained layer is disposed on the barrier layer. The passivation layer covers the gate and the strained layer. The material of the passivation layer differs from that of the strained layer.

Abstract: A semiconductor device includes a channel layer, a barrier layer, source contact and a drain contact, a doped group III-V layer, and a gate electrode. The barrier layer is positioned above the channel layer. The source contact and the drain contact are positioned above the barrier layer. The doped group III-V layer is positioned above the barrier layer and between the first drain contact and the first source contact. The first doped group III-V layer has a first non-vertical sidewall and a second non-vertical sidewall. The gate electrode is positioned above the doped group III-V layer and has a third non-vertical sidewall and a fourth non-vertical sidewall. A horizontal distance from the first non-vertical sidewall to the third non-vertical sidewall is different than a horizontal distance from the second non-vertical sidewall to the fourth non-vertical sidewall.

Abstract: The subject application provides an apparatus and method for measuring dynamic on-resistance of a device under test (DUT) comprising a control terminal electrically connected to an output of a first controlling module being configured to generate a first control signal to switch on and off the DUT. The apparatus comprises a switching device and a second controlling module configured to: receive the first control signal from the first controlling module and generate a second control signal to switch on and off the switching device such that the switching device is turned on later than the DUT for a first time interval and turned off earlier than the DUT for a second time interval.

Abstract: The application relates to a device and method for measuring a high electron mobility transistor. The device provided includes a controller, a protection circuit, a load circuit and a switching circuit electrically connected between the load circuit and the protection circuit. The controller is configured to provide a first control signal having a first value to a semiconductor component at a first time point and provide a second control signal having a second value to the switching circuit at a second time point. The semiconductor component is turned on by the first value of the first control signal, and the switching circuit is turned on by the second value of the second control signal. The second time point is later than the first time point.

Abstract: An electronic device includes a first group III nitride transistor and an electrostatic discharge (ESD) protection circuit. The ESD protection circuit includes a diode and a second transistor. The diode has an anode electrically connected to a gate of the first group III nitride transistor. The second transistor has a drain electrically connected to the gate of the first group III nitride transistor, a gate electrically connected to a cathode of the diode and a source electrically connected to a source of the first group III nitride transistor.

Abstract: A semiconductor device includes a channel layer, a barrier layer, source contact and a drain contact, a doped group III-V layer, and a gate electrode. The barrier layer is positioned above the channel layer. The source contact and the drain contact are positioned above the barrier layer. The doped group III-V layer is positioned above the barrier layer and between the first drain contact and the first source contact. The first doped group III-V layer has a first non-vertical sidewall and a second non-vertical sidewall. The gate electrode is positioned above the doped group III-V layer and has a third non-vertical sidewall and a fourth non-vertical sidewall. A horizontal distance from the first non-vertical sidewall to the third non-vertical sidewall is different than a horizontal distance from the second non-vertical sidewall to the fourth non-vertical sidewall.

Abstract: A nitride semiconductor device includes a semiconductor carrier, a first nitride-based chip, and first conformal connecting structures. The first nitride-based chip is disposed over the semiconductor carrier. The semiconductor carrier has a first planar surface. The first nitride-based chip has a second planar surface, first conductive pads, and first slanted surfaces. The first conductive pads are disposed in the second planar surface. The first slanted surfaces connect the second planar surface to the first planar surface. The first conformal connecting structures are disposed on the first planar surface and the first nitride-based chip. First obtuse angles are formed between the second planar surface and the first slanted surfaces. Each of the first conformal connecting structures covers one of the first slanted surfaces of the first nitride-based chip and one of the first obtuse angles and is electrically connected to the first conductive pads.

Abstract: Semiconductor device structures and methods for manufacturing the same are provided. The semiconductor device structure includes a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a gate electrode, a first electrode, a first via and a second via. The substrate has a first surface and a second surface. The first nitride semiconductor layer is disposed on the first surface of the substrate. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer and has a bandgap exceeding that of the first nitride semiconductor layer. The gate electrode and the first electrode are disposed on the second nitride semiconductor layer. The first via extends from the second surface and is electrically connected to the first electrode. The second via extends from the second surface. The depth of the first via is different from the depth of the second via.