Abstract: Embodiments of the present invention provide a system and method for manufacturing integrated circuit (IC) chip packages. In one embodiment, the integrated circuit (IC) chip package can include an IC chip and a substrate coupled to the IC chip. The substrate can include a glass fiber re-enforced epoxy core, a plurality copper circuitry containing particle re-enforced epoxy layers symmetrically-oriented to each surface of the glass fiber re-enforced epoxy core, and an outermost amorphous glass layer on each surface of the plurality of layers. The IC chip can be coupled to copper circuitry bonded to one of the outermost amorphous glass layers.

Abstract: A process comprises forming a first electrical interconnect structure on a surface of a singulated semiconductor chip having an alignment pattern. The alignment pattern is scanned and stored in a scanning device prior to application of a curable underfill coating to the surface of the singulated semiconductor chip. This is followed by applying a curable underfill coating to the surface of the singulated semiconductor chip to produce a coated semiconductor chip. The process also includes a step of delivering the scanned and stored alignment pattern to an alignment and joining device positioned adjacent to and operatively associated with a substrate having a second electrical interconnect structure alignable to make electrical contact with the first electrical interconnect structure.

Abstract: A process and system for determining alignment data for features on wafers or chips when a wafer or chip is substantially coated by an over bump applied material, e.g. a resin or film, and using that data to align the wafers or chips for subsequent operations such as dicing or joining. Position data for alignment is produced by identifying a location of an at least partially obscured feature by varying the depth of focus upon a work piece to determine an SNR approximating a maximum value from an image captured by optical scanning. An SNR above a threshold value can be employed.

Abstract: A method of stacking a chip, including an integrated circuit, onto a substrate including applying an anisotropic conductive film (ACF) or a solder-filled conductive film onto a surface thereof, the surface being configured to electrically couple to the film, placing the chip onto the film, the chip being configured to electrically couple to the film, compressively pressurizing the chip, the film and the surface such that the chip is electrically coupled to the surface via the film,, testing the chip to determine whether the chip is operating normally, reworking the placement of the chip onto the film and repeating the compressive pressurization if the chip is determined to not be operating normally, repeating the testing to determine whether the chip is operating normally, and once the chip is determined to be operating normally, bonding the chip, the film and the surface.

Abstract: A process of fabricating wafer-level underfilled microelectronic packages using over-bump application of a self-fluxing resin to a wafer, b-staging of the resin, dicing of the coated wafer, and joining the diced chips to substrates producing wafer-level underfilled microelectronic flip-chip packages. Moreover, provided are microelectronic packages, which are produced in accordance with the inventive process.

Abstract: Improved interconnects are produced by injection molded solder which fills mold arrays with molten solder so that columns that have much greater height to width aspect ratios greater than one are formed, rather than conventional flip chip bumps. The columns may have filler particles or reinforcing conductors therein. In the interconnect structures produced, the cost and time of a subsequent underfill step is reduced or avoided. The problem of incompatibility with optical interconnects between chips because underfills require high loading of silica fillers which scatter light, is solved, thus allowing flip chips to incorporate optical interconnects.

Abstract: A semiconductor wafer having alignment marks a sufficient distance from the outer wafer edge that reference dicing channels and a method for same. A process for dicing WLUF coated wafers into singulated chips using said alignment marks on the outer edge of the wafer.

Abstract: A method for measuring the fracture and fatigue crack growth behavior of a material includes heating at least one sample having a first end and a second end and a pre-applied crack between the first end and the second end; heating a fixture having a lower coefficient of thermal expansion than said at least one sample; attaching the first end and the second end of the at least one sample to the fixture; cooling the at least one sample and fixture; recording the temperature at which propagation of the pre-applied crack through the width of the at least one sample occurs as the critical fracture temperature; for a plurality of samples, each sample having a different ratio of pre-applied crack length to sample width, determining the critical fracture temperature as a function of said ratio; and ranking materials by the critical fracture temperature.

Abstract: A single-mode optical waveguide with a core, surrounded by a cladding consisting of an inner soft layer and an outer harder layer is described. The outer layer has a grating structure on its inner surface, whose spatial frequency is the same as that of the guided mode. The thickness of the inner cladding is sufficient to keep the grating outside the mode field in undeformed regions of the waveguide, so that normally no out-coupling of the light results. Connections are made by crossing two such waveguides at an angle and pressing them together. This results in deformation of the two waveguides such that the gratings are brought into proximity with the cores. Light is coupled out of one waveguide and into the other in the deformed region, resulting in a self-aligning optical connection. The out-coupled light propagates normal to the waveguide axis, so errors in the crossing angle cause little change in efficiency.

Abstract: The present disclosure relates generally to semiconductor, integrated circuits, and particularly, but not by way of limitation, to centrifugal methods of filling high-aspect ratio vias and trenches with powders, pastes, suspensions of materials to act as any of a conducting, structural support, or protective member of an electronic component.

Abstract: A method of manufacturing a thermal paste, in which the method includes feeding the thermal paste into a chamber of an extruder; mixing the thermal paste at elevated temperatures; de-airing the thermal paste; and extruding the thermal paste out of the chamber through a die as a pre-form or into a cartridge, such that air channels and pseudo-grain boundaries are prevented from forming in the thermal paste.

Abstract: The present disclosure relates generally to semiconductor, integrated circuits, and particularly, but not by way of limitation, to centrifugal methods of filling high-aspect ratio vias and trenches with powders, pastes, suspensions of materials to act as any of a conducting, structural support, or protective member of an electronic component.

Abstract: A semiconductor wafer and the process for aligning wafer level underfill material coated chips with a substrate via alignment marks made visible through laser dicing.

Abstract: Techniques for providing electrical connections are provided. In one aspect, an electrical connecting device is provided which comprises a plurality of compressible contacts; and a downstop structure surrounding at least a portion of one or more of the contacts, limiting compression of the contacts, and being configured to limit interaction between the contacts. The electrical connecting device may be further configured to have the plurality of compressible contacts have a first coefficient of thermal expansion and the downstop structure have a second coefficient of thermal expansion, the first coefficient of thermal expansion being substantially similar to the second coefficient of thermal expansion.

Abstract: A physically secure processing assembly is provided that includes dies mounted on a substrate so as to sandwich the electrical contacts of the dies between the dies and the substrate. The substrate is provided with substrate contacts and conductive pathways that are electrically coupled to the die contacts and extend through the substrate. Electrical conductors surround the conductive pathways. A monitoring circuit detects a break in continuity of one or more of the electrical conductors, and preferably renders the assembly inoperable. Preferably, an epoxy encapsulation is provided to prevent probing tools from being able to reach the die or substrate contacts.

Abstract: A reversible thermal thickening grease for microelectronic packages, in which the grease contains filler particles; at least one polymer; and a binder; in which the filler particles are dispersed within the binder, in which one or more segments of the at least one polymer may be attached to the filler particles prior to dispersion in the binder, and in which the polymer collapses at temperatures below a Theta temperature and swells at temperatures above a Theta temperature. During the operation of a microelectronic package, grease pump-out and air proliferation are minimized with use of the reversible thermal thickening grease, while grease fluidity is retained under repetitive thermal stresses.

Abstract: A single-mode optical waveguide with a core, surrounded by a cladding consisting of an inner soft layer and an outer harder layer is described. The outer layer has a grating structure on its inner surface, whose spatial frequency is the same as that of the guided mode. The thickness of the inner cladding is sufficient to keep the grating outside the mode field in undeformed regions of the waveguide, so that normally no out-coupling of the light results. Connections are made by crossing two such waveguides at an angle and pressing them together. This results in deformation of the two waveguides such that the gratings are brought into proximity with the cores. Light is coupled out of one waveguide and into the other in the deformed region, resulting in a self-aligning optical connection. The out-coupled light propagates normal to the waveguide axis, so errors in the crossing angle cause little change in efficiency.

Abstract: A physically secure processing assembly is provided that includes dies mounted on a substrate so as to sandwich the electrical contacts of the dies between the dies and the substrate. The substrate is provided with substrate contacts and conductive pathways that are electrically coupled to the die contacts and extend through the substrate. Electrical conductors surround the conductive pathways. A monitoring circuit detects a break in continuity of one or more of the electrical conductors, and preferably renders the assembly inoperable. Preferably, an epoxy encapsulation is provided to prevent probing tools from being able to reach the die or substrate contacts.

Abstract: A heat transfer control structure and a method for fabrication thereof includes at least one heat transfer control layer interposed between and contacting a heat source material and a heat sink material. The at least one heat transfer control layer is selected predicated upon thermal phonon spectra overlap between the heat source material, the at least one heat transfer control layer and the heat sink material. The at least one heat transfer control layer may enhance or retard heat transfer between the heat source material and the heat sink material. The at least one heat transfer control layer may be selected based upon a value of a thermal phonon correlating parameter such as a Debye temperature, a density or a lattice constant.

Abstract: A physically secure processing assembly is provided that includes dies mounted on a substrate so as to sandwich the electrical contacts of the dies between the dies and the substrate. The substrate is provided with substrate contacts and conductive pathways that are electrically coupled to the die contacts and extend through the substrate. Electrical conductors surround the conductive pathways. A monitoring circuit detects a break in continuity of one or more of the electrical conductors, and preferably renders the assembly inoperable. Preferably, an epoxy encapsulation is provided to prevent probing tools from being able to reach the die or substrate contacts.