Abstract: A protection circuit for an integrated circuit product die or die-let (die-let) is responsive to whether the die-let has undergone a dicing operation or not. A test circuit on the die-let's semiconductor wafer can test and/or configure the die-let. After the dicing operation, the protection circuit generates a signal to isolate the cut input lines from the test circuit to prevent any interference with the normal operation of the integrated circuit product die-let.

Abstract: A low power voltage level shifter circuit in which current is limited through at least one of a plurality of CMOS logic circuits, one of which receives input signals within a first voltage level and is connected between a first upper and lower power supply, a second of which transmits shifted output signals within a second voltage level and is connected between a second upper and lower power supply. There is at least one current-limiting MOS transistor connected between at one of the CMOS logic circuits and one of its power supplies. Typically, there is at least one current-limiting MOS transistor between the second CMOS logic circuit which transmits the shifted output signals which have a larger range than that of the input signals. A second current through the at least one current-limiting MOS transistor mirrors a set current through a first MOS transistor so that power consumed by the CMOS logic circuit during switching is limited.

Abstract: An apparatus including a screen capable of separating solids from a liquid-solid mixture and a first probe disposed beneath the screen. The first probe is provided to determine a position of a beach between the liquid-solid mixture and separated solids. The apparatus may measure a property of a local volume of a probe disposed beneath a first separator deck. The probe may then send a first signal to database. Based on the signal a location of a beach may be determined.

Abstract: An MTP (Many Times Programmable) memory cell for integrated circuit memory arrays is described. The cell includes an MTP device and a thyristor interconnected so that the MTP device triggers the thyristor to turn on during a Read or Verify operation. The difference in threshold voltages between a data memory cell and a reference memory cell is used to determine the information in the data memory cell. Different memory cell structures may be constructed for different memory array requirements.

Abstract: A protection circuit for an integrated circuit product die or die-let (die-let) is responsive to whether the die-let has undergone a dicing operation or not. A test circuit on the die-let's semiconductor wafer can test and/or configure the die-let. After the dicing operation, the protection circuit generates a signal to isolate the cut input lines from the test circuit to prevent any interference with the normal operation of the integrated circuit product die-let.

Abstract: A method, apparatus and system for flowing a fluid from an inlet flush nozzle onto tiered plates in a trough is provided. Material may fall from a deck in a vibratory separator, such as a shale shaker, into the trough, which is attached to the separator. The trough has a main inlet and the inlet flush nozzle that opens to tiered plates. An external pipe may feed the fluid into the main inlet and the inlet flush nozzle to lubricate the tiered plates in the trough. Material falling from the vibratory separator may float on the fluid to flow toward an outlet of the trough. A single plate with perforations may be used instead of the tiered plates to permit the fluid to penetrate the perforations to suspend the material, allowing the material to flow across the single plate to an outlet.

Abstract: An apparatus includes a vibratory separator with a top deck, a middle deck, and a bottom deck, and a collection trough coupled to at least one of the top deck, the middle deck, and the bottom deck. The collection trough includes a collection container having an inlet configured to receive a material retained on the at least one of the top deck, the middle deck, and the bottom deck, and a sloped surface configured to guide the material from the inlet to an outlet of the collection container, and a pressure differential generator disposed proximate the outlet of the collection container.

Abstract: An MTP (Many Times Programmable) memory cell for integrated circuit memory arrays is described. The cell includes an MTP device and a thyristor interconnected so that the MTP device triggers the thyristor to turn on during a Read or Verify operation. The difference in threshold voltages between a data memory cell and a reference memory cell is used to determine the information in the data memory cell. Different memory cell structures may be constructed for different memory array requirements.

Abstract: A low power consuming read circuit for a memory array is disclosed. The circuit is particularly useful in applications where oxide breakdown one-time programmable memory is integrated into a system having low power available from the power sources supplying the system.

Abstract: A system having a screen having an upper side and a lower side for separating drill cuttings and drilling fluid within a vibratory separator; a tray positioned below the screen for receiving the drilling fluid from the screen; a pressure differential generator coupled to the tray, the pressure differential generator configured to create a pressure differential between the upper side and the lower side through the screen to enhance the flow of drilling fluid through the screen; and a hose assembly coupling the pressure differential generator to a coupler, an inlet of the coupler being arranged perpendicularly between a first outlet coupled to a mist eliminator and a second outlet coupled to a tank.

Abstract: An MTP (Many Times Programmable) memory cell for integrated circuit memory arrays is described. The cell includes an MTP device and a thyristor interconnected so that the MTP device triggers the thyristor to turn on during a Read or Verify operation. The difference in threshold voltages between a data memory cell and a reference memory cell is used to determine the information in the data memory cell. Different memory cell structures may be constructed for different memory array requirements.

Abstract: A low power consuming read circuit for a memory array is disclosed. The circuit is particularly useful in applications where oxide breakdown one-time programmable memory is integrated into a system having low power available from the power sources supplying the system.

Abstract: An MTP (Many Times Programmable) memory cell for integrated circuit memory arrays is described. The cell includes an MTP device and a thyristor interconnected so that the MTP device triggers the thyristor to turn on during a Read or Verify operation. The difference in threshold voltages between a data memory cell and a reference memory cell is used to determine the information in the data memory cell. Different memory cell structures may be constructed for different memory array requirements.

Abstract: An MTP (Many Times Programmable) memory cell for integrated circuit memory arrays is described. The cell includes an MTP device and a thyristor interconnected so that the MTP device triggers the thyristor to turn on during a Read or Verify operation. The difference in threshold voltages between a data memory cell and a reference memory cell is used to determine the information in the data memory cell. Different memory cell structures may be constructed for different memory array requirements.

Abstract: An apparatus includes a vibratory separator having a first deck, a second deck, and a third deck, and a collection trough coupled to at least one of the first deck, the second deck and the third deck. The collection trough includes a conveying apparatus configured to convey a material in the collection trough to an outlet of the collection trough disposed proximate a first end of the collection trough.

Abstract: The present disclosure relates to inhibitor of Sun1 for treatment of laminopathies and to Sun1 as markers indicative of a patient's responsiveness to treatment, enabling improved prediction of a patient's risk, monitoring of laminopathies.

Abstract: A process for disinfecting a treatment fluid is disclosed, including the step of admixing an aqueous solution comprising two or more oxidants generated via electrolysis of a salt solution with a treatment fluid. The mixed oxidants may be generated on site, using a containerized system.

Abstract: The present invention relates to a polypeptide or a product comprising said polypeptide for use in the treatment and/or prevention of a fungal infection caused by Malassezia spp. and/or a Malassezia spp associated condition wherein the polypeptide comprises a sequence of about 25 to 200 amino acids wherein substantially all of the amino acids in said sequence are lysine; pharmaceutical compositions comprising said polypeptide or product and uses thereof.

Abstract: The present invention provides a method of infecting a nail fragment with a fungus, to form an infected nail fragment comprising at least 1×102 fungal colony forming units (cfu) per cm2 of the infected surface(s). There is also provided a method of assessing the efficacy of potential therapeutic compounds in the treatment or prevention of a fungal nail infection. The fungal nail infection may be a dermatophyte, a non-dermatophyte mould or a pathogen.

Abstract: The invention provides coumarin compounds, in particular glycosidic coumarin compounds, useful in the treatment of dermatophyte fungal infections.